L99UDL01 datasheet(47/88 Pages) STMICROELECTRONICS

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DS12511 Rev 5

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L99UDL01

Serial communications

unwanted Status Register clear should occur, as status information is only cleared with a

dedicated bit clear after read.

5.11

Global status byte

The global status byte is a read only register that appears on every SPI transmission on the

SDO pin. Bit definition can be found in the programmers guide.

5.12

Parity

To ensure proper communication every SPI frame has a parity bit (odd). If a parity error is

detected, then the data is discarded and the SPI Error (SPIE) bit in the Global Status Byte is

set. Parity is checked on all incoming frames (SDI) and is generated for all outgoing frames

(SDO).

5.13

Clock monitor

The number of clock pulses for each frame is counted. If this number is incorrect then the

data is discarded and the SPI Error bit in the Global Status Byte as well as the SPI_FAIL bit

in register 10H are set. Note: This feature prevents this SPI bus from being daisy chained.

Providing no SCK edge during a CSN low to high phase is not recognized as an SPIE.

For a SPI Burst Read also the SPI Data Length plus multiple numbers of Payload SCK

edges are assumed as a valid communication.

5.14

CSN timeout, (tCSN)

By pulling CSN low the SDO is set active and leaves its Tristate condition. To ensure

communication between other SPI devices within the same bus even in case of CSN stuck

@ low a CSN timeout is implemented. By pulling CSN low an internal timer is started. After

timer end is reached the actual communication is rejected and the SDO is set to tri-state

condition. This error (CSN timeout, tCSN) is not reported in any specific status register.

5.15

Burst read

Burst read is used to perform a device internal memory dump to the SPI Master. The start of

the Burst Read is like a normal Read Operation. The difference is, that after the SPI Data

Length the CSN is not pulled high and the SCK will be continuously clocked. When the

normal SCK max count is reached (SPI Data Length) the consecutive addressed data will

be latched into the shift register. This procedure is performed every time the SCK payload

length is reached.

Burst Read will not overrun 3FH. SCK cycles that extend the address beyond 3FH will read

the contents of address 3FH until the transmission is terminated by rising CSN.

The SPI Burst Read is limited by the CSN low timeout.

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