List of figures

Figure 1.

Functional block diagram of L99VR01S ................................................... 2

Figure 2.

Functional block diagram of L99VR01J ................................................... 2

Figure 3.

Pins configuration .................................................................. 3

Figure 4.

Output voltage vs Tj ............................................................... 10

Figure 5.

Output voltage vs VS .............................................................. 10

Figure 6.

Drop voltage vs output current ........................................................ 10

Figure 7.

Current consumption vs output current .................................................. 10

Figure 8.

Current consumption vs input voltage (Io < 1mA) ........................................... 10

Figure 9.

Current consumption vs input voltage (Io = 50 mA) .......................................... 10

Figure 10.

Current consumption vs input voltage (Io= 100 mA) ......................................... 11

Figure 11.

Short-circuit current vs Tj (Ishort pin floating) .............................................. 11

Figure 12.

Short-circuit current vs Tj (Ishort pin tied to GND) ........................................... 11

Figure 13.

Short-circuit current vs input voltage .................................................... 11

Figure 14.

Output voltage vs enable voltage (VO =0.8 V) ............................................. 11

Figure 15.

Output voltage vs enable voltage (VO =1.2 V) ............................................. 11

Figure 16.

Output voltage vs enable voltage (VO =1.5 V) .............................................. 12

Figure 17.

Output voltage vs enable voltage (VO =1.8 V) ............................................. 12

Figure 18.

Output voltage vs enable voltage (VO =2.5 V) ............................................. 12

Figure 19.

Output voltage vs enable voltage (VO =2.8 V) .............................................. 12

Figure 20.

Output voltage vs enable voltage (VO =3.3 V) ............................................. 12

Figure 21.

Output voltage vs enable voltage (VO =5 V) ............................................... 12

Figure 22.

VEn_high vs Tj .................................................................. 12

Figure 23.

VEn_low vs Tj ................................................................... 12

Figure 24.

PSRR ......................................................................... 13

Figure 25.

Load regulation test circuit ........................................................... 14

Figure 26.

Maximum load variation response ..................................................... 14

Figure 27.

Application schematic .............................................................. 15

Figure 28.

Application schematic – Post regulation .................................................. 15

Figure 29.

Behavior of output current versus regulated voltage Vo ....................................... 16

Figure 30.

Ishort versus Rsh ................................................................. 17

Figure 31.

Example of output voltage selection .................................................... 18

Figure 32.

Typical example of enable control ...................................................... 18

Figure 33.

Reset timing diagram............................................................... 19

Figure 34.

Thermal warning diagram............................................................ 19

Figure 35.

Square wave on TW pin generated during an overvoltage ..................................... 20

Figure 36.

Warning signal caused by overvoltage and thermal warning on TW pin ............................ 20

Figure 37.

Undervoltage lockout on output voltage .................................................. 21

Figure 38.

Typical application................................................................. 23

Figure 39.

PowerSSO-12 PC board ............................................................ 24

Figure 40.

Rthj-amb versus PCB copper area in open box free air condition.................................. 25

Figure 41.

PowerSSO-12 thermal impedance junction ambient single pulse................................. 25

Figure 42.

Thermal fitting model of a Vreg in PowerSSO-12 ............................................ 26

Figure 43.

SO-8 PC board................................................................... 27

Figure 44.

Rthj-amb vs PCB copper area in open box free air condition.................................... 28

Figure 45.

SO-8 thermal impedance junction ambient single pulse ....................................... 28

Figure 46.

Thermal fitting model of a Vreg in SO-8 .................................................. 29

Figure 47.

PowerSSO-12 package dimensions .................................................... 30

Figure 48.

SO-8 package dimension............................................................ 31

Figure 49.

PowerSSO-12 tape and reel shipment (suffix “TR”) .......................................... 33

Figure 50.

SO-8 tape and reel shipment (suffix “TR”) ................................................ 34

L99VR01

List of figures

DS13649 - Rev 4

page 39/40