 |
数据搜索系统，热门电子元器件搜索 |
|
|
数据搜索系统，热门电子元器件搜索 |
|
SC16C852LIB 数据表(PDF) 39 Page - NXP Semiconductors |
|
|
|||||||||||||||||||||||||||||
SC16C852LIB 数据表(HTML) 39 Page - NXP Semiconductors |
|
|
39 / 63 page  SC16C852L_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 18 January 2008 39 of 63 NXP Semiconductors SC16C852L 1.8 V dual UART with 128-byte FIFOs and IrDA encoder/decoder 7.20 RS-485 turn-around time delay (RS485TIME) The value in this register controls the turn-around time of the external line transceiver in bit time. In automatic 9-bit mode RTSA/RTSB or DTRA/DTRB pin is used to control the direction of the line driver, after the last bit of data has been shifted out of the transmit shift register the UART will count down the value in this register. When the count value reaches zero, the UART will assert RTSA/RTSB or DTRA/DTRB pin (logic 0) to turn the external RS-485 transceiver around for receiving. 7.21 Advanced Feature Control Register 2 (AFCR2) Table 32. RS-485 programmable turn-around time register bits description Bit Symbol Description 7:0 RS485TIME[7:0] External RS-485 transceiver turn-around time delay. The value represents the bit time at the programmed baud rate. Table 33. Advanced Feature Control Register 2 register bits description Bit Symbol Description 7:6 AFCR2[7:6] reserved 5 AFCR2[5] RTSInvert. Invert RTS or DTR signal in automatic 9-bit mode. logic logic 0 = RTS or DTR is set to 0 by the UART during transmission, and to 1 during reception logic 1 = RTS or DTR is set to 1 by the UART during transmission, and to 0 during reception 4 AFCR2[4] RTSCon. Enable the transmitter to control RTSx or DTRx pin in automatic 9-bit mode. logic logic 0 = transmitter does not control RTSx or DTRx pin logic 1 = transmitter controls RTSx or DTRx pin 3 AFCR2[3] RS485 RTS/DTR. Select RTSx or DTRx pin to control the external transceiver. logic logic 0 = RTSx pin is used to control the external transceiver logic 1 = DTRx pin is used to control the external transceiver 2 AFCR2[2] TXDisable. Disable transmitter logic 0 = transmitter is enabled logic 1 = transmitter is disable 1 AFCR2[1] RXDisable. Disable receiver logic 0 = receiver is enabled logic 1 = receiver is disable 0 AFCR2[0] 9-bitMode. Enable 9-bit mode or Multidrop (RS-485) mode logic logic 0 = normal RS-232 mode logic 1 = enable 9-bit mode |
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Chinese ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
