10 mils

10 mils

40 mils

FR-4

0r ~ 4.5

Keep this

space free

from planes,

traces , pads,

and vias

Ground plane

Power plane

Low-speed traces

High-speed traces

ISO7640FM, ISO7641FM

www.ti.com

SLLSE89G – SEPTEMBER 2011 – REVISED JANUARY 2015

10 Power Supply Recommendations

To ensure reliable operation at all data rates and supply voltages, a 0.1-

μF bypass capacitor is recommended at

input and output supply pins (VCC1 and VCC2). The capacitors should be placed as close to the supply pins as

possible. If only a single primary-side power supply is available in an application, isolated power can be

generated for the secondary-side with the help of a transformer driver such as Texas Instruments' SN6501. For

such applications, detailed power supply design and transformer selection recommendations are available in

SN6501 data sheet (SLLSEA0).

11 Layout

11.1 Layout Guidelines

A minimum of four layers is required to accomplish a low EMI PCB design (see Figure 21). Layer stacking should

be in the following order (top-to-bottom): high-speed signal layer, ground plane, power plane and low-frequency

signal layer.

•

Routing the high-speed traces on the top layer avoids the use of vias (and the introduction of their

inductances) and allows for clean interconnects between the isolator and the transmitter and receiver circuits

of the data link.

•

Placing a solid ground plane next to the high-speed signal layer establishes controlled impedance for

transmission line interconnects and provides an excellent low-inductance path for the return current flow.

•

Placing the power plane next to the ground plane creates additional high-frequency bypass capacitance of

approximately 100 pF/in2.

•

Routing the slower speed control signals on the bottom layer allows for greater flexibility as these signal links

usually have margin to tolerate discontinuities such as vias.

If an additional supply voltage plane or signal layer is needed, add a second power and ground plane system to

the stack to keep it symmetrical. This makes the stack mechanically stable and prevents it from warping. Also the

power and ground plane of each power system can be placed closer together, thus increasing the high-frequency

bypass capacitance significantly.

NOTE

For detailed layout recommendations, see Digital Isolator Design Guide, SLLA284.

11.2 Layout Example

Figure 21. Recommended Layer Stack

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