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ISO6763FDWR 数据表(PDF) 36 Page - Texas Instruments |
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ISO6763FDWR 数据表(HTML) 36 Page - Texas Instruments |
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36 / 50 page ![]() 11.2 Layout Example 0.5 mm maximum from VCC2 Solid ground islands help dissipate heat through PCB Solid supply islands reduce inductance because large peak currents flow into the VCC pin 1 2 3 4 5 7 8 16 15 14 13 12 10 9 VCC2 GND1 VCC1 GND2 11 6 0.5 mm maximum from VCC1 0.1 …F 0.1 …F I/O pins routed through alternate layer with vias Figure 11-1. Layout Example 10 mils 10 mils 40 mils FR-4 0r ~ 4.5 Keep this space free from planes, traces, pads, and vias Ground plane Power plane Low-speed traces High-speed traces Figure 11-2. Four Layer Board Layout Example ISO6760, ISO6761, ISO6762, ISO6763 SLLSFK0E – AUGUST 2021 – REVISED FEBRUARY 2023 www.ti.com 36 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: ISO6760 ISO6761 ISO6762 ISO6763 |
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