VNF9D5F datasheet(4/108 Pages) STMICROELECTRONICS

4 / 108 page

Table 1. Pin functionality description

Pin #

Name

Function

TAB

VCC

Battery connection: this is the backside TAB and is the direct connection to drain Power MOSFET

switches.

1-4

OUTPUT1

Power OUTPUT 1: direct connection to the source Power MOSFET channel 1.

5, 20

N.C.

Not connected pin.

6-8, 25-32

N.C.

Not connected pin.

9, 10

DI0, DI1

Direct input: direct control for OUTx in limp-home mode. Configurable as OR combination with the

relevant SPI OUTx control bit in normal mode.

PWM_CLK

External clock of PWM engine.

CSN

Chip select not (active low): it is the selection pin of the device. It is a CMOS compatible input.

SCK

Serial clock: it is a CMOS compatible input.

SDI

Serial data input: transfers data to be written serially into the device on the SCK rising edge.

SDO

Serial data output: transfers data serially out of the device on the SCK falling edge.

VDD

DC supply input for the SPI interface. 3.3 V and 5 V compatible.

GND

Ground connection: this pin serves as the ground connection for the logic part of the device.

VREG

DC output of internal preregulator (4.7 V) generated from VCC to supply VREG pin and digital

control circuit.

Connect a low ESR capacitor (2 μF) in series with a resistor (120 Ω) close to this pin referenced to

device ground.

STDBY_NOT Standby mode enabler (active low).

21-24

OUTPUT0

Power OUTPUT 0: direct connection to the source Power MOSFET channel 0.

VNF9D5F

Block diagram and pin description

DS13946 - Rev 8

page 4/108

VNF9D5F 数据表(PDF) 4 Page - STMicroelectronics

VNF9D5F 数据表(HTML) 4 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载