I2C bus

TDA7563B

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Doc ID 12733 Rev 6

7.2.4

Acknowledge

The transmitter* puts a resistive HIGH level on the SDA line during the acknowledge clock

pulse (see Figure 31). The receiver**, in order to acknowledge, has to pull-down (LOW) the

SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during this

clock pulse.

* Transmitter

–master (

P) when it writes an address to the TDA7563B

–

slave (TDA7563B) when the

P reads a data byte from TDA7563B

** Receiver

–

slave (TDA7563B) when the

P writes an address to the TDA7563B

–

master (µP) when it reads a data byte from TDA7563B

Figure 29.

Data validity on the I2C bus

Figure 30.

Timing diagram on the I2C bus

Figure 31.

Timing acknowledge clock pulse