SPC560D30L3 datasheet(40/82 Pages) STMICROELECTRONICS

40 / 82 page

Electrical characteristics

SPC560D30x, SPC560D40x

40/82

DS6494 Rev 8

4.9

Power management electrical characteristics

4.9.1

Voltage regulator electrical characteristics

The device implements an internal voltage regulator to generate the low voltage core supply

VDD_LV from the high voltage ballast supply VDD_BV. The regulator itself is supplied by the

common I/O supply VDD. The following supplies are involved:



HV: High voltage external power supply for voltage regulator module. This must be

provided externally through VDD power pin.



BV: High voltage external power supply for internal ballast module. This must be

provided externally through VDD_BV power pin. Voltage values should be aligned with

VDD.



LV: Low voltage internal power supply for core, FMPLL and flash digital logic. This is

generated by the internal voltage regulator but provided outside to connect stability

ttr

CC D

Output transition

time output pin(3)

MEDIUM

configuration

CL = 25 pF,

VDD = 5.0 V ± 10%, PAD3V5V = 0

——

CL = 50 pF,

VDD = 5.0 V ± 10%, PAD3V5V = 0

——

CL = 100 pF,

VDD = 5.0 V ± 10%, PAD3V5V = 0

——

CL = 25 pF,

VDD = 3.3 V ± 10%, PAD3V5V = 1

——

CL = 50 pF,

VDD = 3.3 V ± 10%, PAD3V5V = 1

——

CL = 100 pF,

VDD = 3.3 V ± 10%, PAD3V5V = 1

——

WFRST SR P

RESET input filtered

pulse

——

—

WNFRST SR P

RESET input not

filtered pulse

—

1000

—

|IWPU|CC P

Weak pull-up current

absolute value

VDD = 3.3 V ± 10%, PAD3V5V = 1

—

150

µA

VDD = 5.0 V ± 10%, PAD3V5V = 0

—

150

VDD = 5.0 V ± 10%,

PAD3V5V = 1(4)

—

250

1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified.

2. This is a transient configuration during power-up, up to the end of reset PHASE2 (refer to RGM module section of the

device reference manual).

3. CL includes device and package capacitance (CPKG <5pF).

4. The configuration PAD3V5 = 1 when VDD = 5 V is only transient configuration during power-up. All pads but RESET are

configured in input or in high impedance state.

Table 23. Reset electrical characteristics (continued)

Symbol

Parameter

Conditions(1)

Value

Unit

Min

Typ

Max

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