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STA680 数据表(PDF) 24 Page - STMicroelectronics |
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STA680 数据表(HTML) 24 Page - STMicroelectronics |
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24 / 48 page  Operation and general remarks STA680 24/48 DS5877 Rev 13 Figure 6 shows a simplified version of the internal clock generation unit. Figure 6. Clock generation unit Clock generation unit Some remarks on the clock input pin follow: OSC_IN is always a 1.8 V input pin; CLK_IN, BB1_BCK are 3.3 V; When the clock is fed through the CLK_IN pin, the OSC_IN pin must be connected to ground (and vice versa); The BB1_BCK pin is the bit clock of the digital interface to the baseband Tuner. When this pin is selected as input for the reference clock, the selected clock frequency must be chosen compatibly with the Primary baseband Interface settings (see Section 5.2): – 10.4 MHz = 16 * 650 kHz BBI set to 650 Ksample/s – 10.8 MHz = 16 * 675 kHz BBI set to 675 Ksample/s; When the device reference clock comes from BB1_BCK it is suggested to connect the OSC_IN to ground and to tie the CLK_IN pin to its high value (3.3 V). |
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