STPM01 datasheet(42/60 Pages) STMICROELECTRONICS

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Theory of operation

STPM01

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Doc ID 10853 Rev 8

t1 → t2: Latching phase. Interval value > 2/fCLK

t2 → t3: Data latched, SPI idle. Interval value > 30 ns

t3 → t4: Enable SPI for read operation. Interval value > 30 ns

t4 → t5: Serial clock counter is reset. Interval value > 30 ns

t5 → t6: SPI reset and enabled for read operation. Interval value > 30 ns

t7: Internal data transferred to SDATD

t8: SDATD data is stable and can be read

The system that reads the data record from the STPM01 should check the integrity of each

data record. If the check fails, the reading should be repeated, but this time only the shifting

should be applied otherwise a new data would be latched into transmission latches and

incorrectly read one would be lost.

Normally, each byte is read out as most significant bit (MSB) first. But this can be changed

by setting the MSBF configuration bit in the STPM01 CFL data record. If this is done, each

byte is read out as least significant bit (LSB) first.

8.23

Writing procedure

Each writable bit (configuration and mode bits) has its own 6-bit absolute address. For the

configuration bits, the 6-bit address value corresponds to its decimal value, while for the

mode bits the addresses are the ones indicated in the Mode Signal paragraph.

In order to change the state of some latch one must send to STPM01 a byte of data which is

normal way to send data via SPI. This byte consists of 1-bit data to be latched (MSB),

followed by 6-bit address of destination latch, followed by 1-bit don’t care data (LSB) which

makes total 8 bits of command byte.

For example, if we would like to set the configuration bit 47 (part of the secondary current

channel calibrator) to 0, we must convert the decimal 47 to its 6-bit binary value: 101111.

The byte command will be then composed like this:

1 bit DATA value+6-bits address+1 bit (0 or 1) as depicted in Figure 27. In this case the

binary command will be 01011111 (0x5F) which is the one depicted in the figure or

01011110 (0x5E).

Figure 27.

Timing for writing configuration and mode bits

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