LP2997

SNVS295F – MAY 2004 – REVISED APRIL 2013

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DESCRIPTION

The LP2997 is a linear bus termination regulator designed to meet the JEDEC requirements of SSTL-18. The

output, VTT is capable of sinking and sourcing current while regulating the output voltage equal to VDDQ / 2. The

output stage has been designed to maintain excellent load regulation while preventing shoot through. The

LP2997 also incorporates two distinct power rails that separates the analog circuitry from the power output stage.

This allows a split rail approach to be utilized to decrease internal power dissipation. It also permits the LP2997

to provide a termination solution for the next generation of DDR-SDRAM memory (DDRII).

Pin Descriptions

AVIN AND PVIN AVIN and PVIN are the input supply pins for the LP2997. AVIN is used to supply all the internal control circuitry. PVIN,

however, is used exclusively to provide the rail voltage for the output stage used to create VTT. These pins have the capability to work off

separate supplies, under the condition that AVIN is always greater than or equal to PVIN. For SSTL-18 applications, it is recommended to

connect PVIN to the 1.8V rail used for the memory core and AVIN to a rail within its operating range of 2.2V to 5.5V (typically a 2.5V

supply). PVIN should always be used with either a 1.8V or 2.5V rail. This prevents the thermal limit from tripping because of excessive

internal power dissipation. If the junction temperature exceeds the thermal shutdown than the part will enter a shutdown state identical to

the manual shutdown where VTT is tri-stated and VREF remains active. A lower rail such as 1.5V can be used but it will reduce the maximum

output current, therefore it is not recommended for most termination schemes.

VDDQ VDDQ is the input used to create the internal reference voltage for regulating VTT. The reference voltage is generated from a resistor

divider of two internal 50k

Ω resistors. This ensures that VTT will track VDDQ / 2 precisely. The optimal implementation of VDDQ is as a

remote sense. This can be achieved by connecting VDDQ directly to the 1.8V rail at the DIMM instead of PVIN. This ensures that the

reference voltage tracks the DDR memory rails precisely without a large voltage drop from the power lines. For SSTL-18 applications

VDDQ will be a 1.8V signal, which will create a 0.9V termination voltage at VTT (See Electrical Characteristics Table for exact values of VTT

over temperature).

VSENSE The purpose of the sense pin is to provide improved remote load regulation. In most motherboard applications the termination

resistors will connect to VTT in a long plane. If the output voltage was regulated only at the output of the LP2997 then the long trace will

cause a significant IR drop resulting in a termination voltage lower at one end of the bus than the other. The VSENSE pin can be used to

improve this performance, by connecting it to the middle of the bus. This will provide a better distribution across the entire termination bus.

If remote load regulation is not used then the VSENSE pin must still be connected to VTT. Care should be taken when a long VSENSE trace is

implemented in close proximity to the memory. Noise pickup in the VSENSE trace can cause problems with precise regulation of VTT. A small

0.1uF ceramic capacitor placed next to the VSENSE pin can help filter any high frequency signals and preventing errors.

SHUTDOWN The LP2997 contains an active low shutdown pin that can be used for suspend to RAM functionality. In this condition the VTT

output will tri-state while the VREF output remains active providing a constant reference signal for the memory and chipset. During shutdown

VTT should not be exposed to voltages that exceed PVIN. With the shutdown pin asserted low the quiescent current of the LP2997 will drop,

however, VDDQ will always maintain its constant impedance of 100k

Ω for generating the internal reference. Therefore, to calculate the total

power loss in shutdown both currents need to be considered. For more information refer to the Thermal Dissipation section. The shutdown

pin also has an internal pull-up current; therefore, to turn the part on the shutdown pin can either be connected to AVIN or left open

VREF VREF provides the buffered output of the internal reference voltage VDDQ / 2. This output should be used to provide the reference

voltage for the Northbridge chipset and memory. Since these inputs are typically an extremely high impedance, there should be little current

drawn from VREF. For improved performance, an output bypass capacitor can be used, located close to the pin, to help with noise. A

ceramic capacitor in the range of 0.1 µF to 0.01 µF is recommended. This output remains active during the shutdown state and thermal

shutdown events for the suspend to RAM functionality.

VTT VTT is the regulated output that is used to terminate the bus resistors. It is capable of sinking and sourcing current while regulating the

output precisely to VDDQ / 2. The LP2997 is designed to handle continuous currents of up to +/- 0.5A with excellent load regulation. If a

transient is expected to last above the maximum continuous current rating for a significant amount of time, then the bulk output capacitor

should be sized large enough to prevent an excessive voltage drop. If the LP2997 is to operate in elevated temperatures for long durations

care should be taken to ensure that the maximum junction temperature is not exceeded. Proper thermal de-rating should always be used.

(Please refer to the Thermal Dissipation section) If the junction temperature exceeds the thermal shutdown point than VTT will tri-state until

the part returns below the temperature hysteresis trip-point

COMPONENT SELECTIONS

INPUT CAPACITOR

The LP2997 does not require a capacitor for input stability, but it is recommended for improved performance

during large load transients to prevent the input rail from dropping. The input capacitor should be located as

close as possible to the PVIN pin. Several recommendations exist dependent on the application required. A

typical value recommended for AL electrolytic capacitors is 22 µF. Ceramic capacitors can also be used. A value

in the range of 10 µF with X5R or better would be an ideal choice. The input capacitance can be reduced if the

LP2997 is placed close to the bulk capacitance from the output of the 1.8V DC-DC converter. For the AVIN pin, a

small 0.1uF ceramic capacitor is sufficient to prevent excessive noise from coupling into the device.

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