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LP2992IM5X-3.3/NO.B 数据表(PDF) 5 Page - Texas Instruments

部件名 LP2992IM5X-3.3/NO.B
功能描述  LP2992 Micropower, 250mA, Low-Noise, Ultra-Low-Dropout Regulator in SOT-23 and WSON Packages Designed for Use With Very Low-ESR Output Capacitors
PDF  43 Pages
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制造商  TI2 [Texas Instruments]
网页  https://www.ti.com
标志 TI2 - Texas Instruments

LP2992IM5X-3.3/NO.B 数据表(HTML) 5 Page - Texas Instruments

  LP2992IM5X-3.3/NO.B Datasheet HTML 1Page - Texas Instruments LP2992IM5X-3.3/NO.B Datasheet HTML 2Page - Texas Instruments LP2992IM5X-3.3/NO.B Datasheet HTML 3Page - Texas Instruments LP2992IM5X-3.3/NO.B Datasheet HTML 4Page - Texas Instruments LP2992IM5X-3.3/NO.B Datasheet HTML 5Page - Texas Instruments LP2992IM5X-3.3/NO.B Datasheet HTML 6Page - Texas Instruments LP2992IM5X-3.3/NO.B Datasheet HTML 7Page - Texas Instruments LP2992IM5X-3.3/NO.B Datasheet HTML 8Page - Texas Instruments LP2992IM5X-3.3/NO.B Datasheet HTML 9Page - Texas Instruments Next Button
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5.4 Thermal Information
THERMAL METRIC (2) (1)
Legacy Chip
Only
Legacy Chip
New Chip
UNIT
NGD (WSON)
(3)
DBV
(SOT23-5)
DBV
(SOT23-5)
6 PINS
5 PINS
5 PINS
RθJA
Junction-to-ambient thermal resistance
72.3
169.7
178.6
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
81.6
122.6
77.9
°C/W
RθJB
Junction-to-board thermal resistance
39.5
29.9
47.2
°C/W
ψJT
Junction-to-top characterization parameter
2
16.7
15.9
°C/W
ψJB
Junction-to-board characterization parameter
39.2
29.4
46.9
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
11.6
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
note.
(2)
Thermal performance results are based on the JEDEC standard of 2s2p PCB configuration. These thermal metric parameters can be
further improved by 35-55% based on thermally optimized PCB layout designs. See the analysis of the Impact of board layout on LDO
thermal performance application report.
(3)
The PCB for the NGD (WSON) package RθJA includes two (2) thermal vias under the exposed thermal pad per EIA/JEDEC
JESD51-5.
5.5 Electrical Characteristics
specified at TJ = 25°C, VIN = VOUT(nom) + 1.0 V or VIN = 2.5 V (whichever is greater), IOUT = 1 mA, VON/OFF = 2 V, CIN = 1.0
µF, and COUT = 2.2 µF (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP MAX UNIT
∆VOUT
Output voltage tolerance
IL = 1 mA
Legacy chip
(standard
grade)
–1.5
1.5
%
Legacy chip
(A grade)
–1.0
1.0
New chip
–0.5
0.5
1 mA ≤ IL ≤ 50 mA
Legacy chip
(standard
grade)
–2.5
2.5
Legacy chip
(A grade)
–1.5
1.5
New chip
–0.5
0.5
1 mA ≤ IL ≤ 50 mA, –40°C ≤ TJ ≤ 125°C
Legacy chip
(standard
grade)
–3.5
3.5
Legacy chip
(A grade)
–2.5
2.5
New chip
–1
1
1 mA ≤ IL ≤ 250 mA
Legacy chip
(standard
grade)
–4
4
Legacy chip
(A grade)
–3.5
3.5
New chip
–0.5
0.5
1 mA ≤ IL ≤ 250 mA, –40°C ≤ TJ ≤ 125°C
Legacy chip
(standard
grade)
–5
5
Legacy chip
(A grade)
–4.5
4.5
New chip
–1
1
www.ti.com
LP2992
SNVS171L – NOVEMBER 2001 – REVISED FEBRUARY 2025
Copyright © 2025 Texas Instruments Incorporated
Submit Document Feedback
5
Product Folder Links: LP2992



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