4 Pin Configuration and Functions

OUT

BYPASS

1

2

3

4

5

IN

GND

ON/OFF

Figure 4-1. DBV Package, 5-Pin SOT-23 (Top View)

Figure 4-2. NGD Package, 6-Pin WSON (Top View) (Legacy Chip)

Table 4-1. Pin Functions

PIN

TYPE

DESCRIPTION

NAME

DBV

NGD (Legacy

chip only)

BYPASS

4

1

I

BYPASS pin to achieve low noise performance. Connecting an external capacitor

between BYPASS pin and ground reduces reference voltage noise. See the

Recommended Operating Conditions table for more information.

GND

2

2

—

Ground

ON/OFF

3

3

I

Enable pin for the LDO. Driving the ON/OFF pin high enables the device. Driving

this pin low disables the device. High and low thresholds are listed in the Electrical

Characteristics table. Tie this pin to VIN if unused.

IN

1

4

I

Input supply pin. Use a capacitor with a value of 1µF or larger from this pin

to ground. See the Input and Output Capacitor Requirements section for more

information.

OUT

5

6

O

Output of the regulator. Use a capacitor with a value of 2.2µF or larger from this pin

to ground(1). See the Input and Output Capacitor Requirements section for more

information.

N/C

–

5

–

No internal connection. Connect to GND or leave open. (Legacy chip only)

DAP

–

Exposed

thermal pad

–

The exposed die attach pad on the bottom of the package must be connected to

a copper thermal pad on the PCB at ground potential. Connect to ground potential

or leave floating. Do not connect to any potential other than the same ground

potential seen at device pin 2. (Legacy chip only)

(1)

The nominal output capacitance must be greater than 1μF. Throughout this document, the nominal derating on these capacitors is

50%. Make sure that the effective capacitance at the pin is greater than 1μF.

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LP2992

SNVS171L – NOVEMBER 2001 – REVISED FEBRUARY 2025

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