M41T82 datasheet(21/64 Pages) STMICROELECTRONICS

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M41T82, M41T83

Clock operation

3.1.2

Accessing the device

The M41T82/83 is comprised of 32 addresses which provide access to registers for time

and date, digital and analog calibration, two alarms, watchdog, flags, timer, squarewave

(M41T83 only) and NVRAM. The clock and alarm parameters are in binary coded decimal

(BCD) format. The calibration, timer, watchdog, and squarewave parameters are in a binary

format.

In the case of the M41T82 and M41T83, at the start of each read or write serial transfer, the

counters are automatically copied to the buffer registers. In the event of a write to any

back into the counters thus revising the date/time. Any of the eight clock registers

(addresses 0-7) not updated during the transfer will have its old value written back into the

counters. For example, if only the seconds value is revised, the other seven counters will

end up with the same values they had at the start of the serial transfer.

However, writes which do not affect the clock registers - that is, a write only to the non-clock

registers (addresses 0x08 to 0x1F) - will not cause the buffer registers to be copied back to

the counters. The counters are only updated if a register in the range 0-7 was written.

Whenever the RTC registers (addresses 0-7) are written, the divider chain from the

oscillator is reset.

3.2

Halt bit (HT) operation

When the part is powered down into battery backup mode, a control bit, called the Halt or

HT bit, is set automatically. This inhibits any subsequent transfers from the counters to the

buffer registers thereby freezing in the buffer registers the time/date of the last access of the

part.

Repeated reads of the clock registers will return the same value. After the HT bit is cleared,

by writing bit 6 of address 0x0C to 0, the next read of the RTC will return the present time.

Note:

Writes to the RTC registers (addresses 0-7) with the HT bit set can cause time corruption.

Since the buffer registers contain the time of the last access prior to the HT bit being set,

any write in the address range 0-7 will result in the time of the last access being copied back

into the counters.

Example: The last access was November 17, 2009, at 16:15:07.77. The system later

powered down thus setting the HT bit and freezing that value in the buffers. Later, on

December 18, 2009, at 03:22:43.35, the system is powered up and the user writes the

seconds to 46 without first clearing the HT bit. At the end of the serial transfer, the old

time/date, with the seconds modified to 46, will be written back into the clock registers

thereby corrupting them. The new, wrong time will be November 17, 2009, at 16:15:46.77.

This makes it appear the RTC lost time during the power outage.

Thus, at power-up, the user should always clear the HT bit (write bit 6 to 0 at address 0x0C)

before writing to any address in the range 0-7.

A typical power-up flow is to read the time of last access, then clear the HT bit, then read the

current time.

M41T82 数据表(PDF) 21 Page - STMicroelectronics

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