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M41TC8025AMC7F 数据表(PDF) 9 Page - STMicroelectronics

部件名 M41TC8025AMC7F
功能描述  Highly accurate, temperature-compensated serial real-time clock (RTC) with embedded crystal
PDF  41 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

M41TC8025AMC7F 数据表(HTML) 9 Page - STMicroelectronics

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M41TC8025
Operation
2.1.6
Alarm interrupt
The user can set the alarm interrupt condition in the alarm date, day, hours, and minutes
registers. Once the current clock and calendar match the alarm condition, the alarm is
activated so that the IRQ pin will be pulled low if enabled (bit AIE=1) and the flag bit (AF) will
be set to 1 to indicate the alarm occurrence (no auto-clear of the IRQ pin nor the flag bit).
Refer to Section 2.8: Alarm interrupt function on page 25 for a detailed description.
2.2
Two-wire I2C bus characteristics
The bus is intended for communication between different ICs. It consists of two lines: a
bidirectional data signal (SDA) and a clock signal (SCL). Both the SDA and SCL lines must
be connected to a positive supply voltage via a pull-up resistor.
The following protocol has been defined:
Data transfer may be initiated only when the bus is not busy.
During data transfer, the data line must remain stable whenever the clock line is high.
Changes in the data line, while the clock line is high, will be interpreted as control
signals.
Accordingly, the following bus conditions have been defined:
2.2.1
Bus not busy
Both data and clock lines remain high.
2.2.2
Start data transfer
A change in the state of the data line, from high to low, while the clock is high, defines the
START condition.
2.2.3
Stop data transfer
A change in the state of the data line, from low to high, while the clock is high, defines the
STOP condition.
2.2.4
Data valid
The state of the data line represents valid data when after a START condition; the data line
is stable for the duration of the high period of the clock signal. The data on the line may be
changed during the low period of the clock signal. There is one clock pulse per bit of data.
Each data transfer is initiated with a START condition and terminated with a STOP
condition. The number of data bytes transferred between the START and STOP conditions
is not limited. The information is transmitted byte-wide and each receiver acknowledges with
a ninth bit.
By definition a device that gives out a message is called "transmitter," the receiving device
that gets the message is called "receiver." The device that controls the message is called
"master." The devices that are controlled by the master are called "slaves."
Obsolete
Product(s)
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