LP5569ARTWR datasheet(8/93 Pages) TI2

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LP5569

SNVSAP8A – JULY 2017 – REVISED SEPTEMBER 2017

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7.10 Serial-Bus Timing Requirements (SDA, SCL), See Figure 1

2C fast mode

MIN

MAX

UNIT

ƒSCL

Clock frequency

400

kHz

Hold time (repeated) START condition

0.6

µs

Clock low time

1.3

µs

Clock high time

600

Setup time for a repeated START condition

600

Data hold time

Data setup time

100

Rise time of SDA and SCL

20 + 0.1Cb

300

Fall time of SDA and SCL

15 + 0.1Cb

300

Setup time for STOP condition

600

Bus-free time between a STOP and a START condition

1.3

µs

Capacitive load for each bus line

200

7.11 External Clock Timing Requirements (CLK), See Figure 2

over operating ambient temperature range (unless otherwise noted)

MIN

TYP

MAX

UNIT

ƒCLK

Clock frequency

32.7

kHz

tCLKH

High time

µs

tCLKL

Low time

µs

Clock rise time, 10% rising edge to 90% rising edge

µs

Clock fall time, 90% falling edge to 10% falling edge

µs

Figure 1. Timing Parameters

Figure 2. External Clock Signal

LP5569ARTWR 数据表(PDF) 8 Page - Texas Instruments

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