IS25LP256D-RHLA3-TR datasheet(146/179 Pages) ISSI

146 / 179 page

IS25LP256D

IS25WP256D

Integrated Silicon Solution, Inc.- www.issi.com

146

Rev A15

08/05/2024

8.51 READ DYB OPERATION (RDDYB, FAh or 4RDDYB, E0h)

FAh (EXTADD=0) is followed by a 3-byte address (A23-A0) or

• FAh (EXTADD=1) is followed by a 4-byte address (A31-A0) or

• E0h is followed by a 4-byte address (A31-A0)

The instruction is used to read Dynamic Protection Bit (DYB) status of the given sector/block. The instruction code

is entered first, followed by the 24-bit or 32-bit address selecting location zero within the desired sector/block as

above. Then the 8-bit DYB access register contents are shifted out. Each bit (SPI) or four bits (QPI) are shifted out

at the SCK frequency by the falling edge of the SCK signal. It is possible to read the same DYB access register

continuously by providing multiples of eight bits. The address of the DYB register does not increment so this is not

a means to read the entire DYB array. Each location must be read with a separate Read DYB instruction. The

maximum operating clock frequency for READ command is the same with Fast Read Operation.

Note: The high order address bits not used by 256M/128M must be zero. Data must be either 00h (protected) or FFh

(unprotected).

Figure 8.116 Read DYB Sequence In SPI Mode (FAh [EXTADD=0], 3-byte address)

Instruction = FAh

CE #

SCK

...

Mode 3

Mode 0

3-byte Address

IS25LP256D-RHLA3-TR 数据表(PDF) 146 Page - Integrated Silicon Solution, Inc