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IS25LP256D-RHLA3-TR 数据表(PDF) 160 Page - Integrated Silicon Solution, Inc |
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IS25LP256D-RHLA3-TR 数据表(HTML) 160 Page - Integrated Silicon Solution, Inc |
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160 / 179 page  IS25LP256D IS25WP256D Integrated Silicon Solution, Inc.- www.issi.com 160 Rev A15 08/05/2024 8.62 PROGRAM PASSWORD OPERATION (PGPWD, E8h) Before the Program Password (PGPWD) command can be accepted by the device, a Write Enable (WREN) command must be issued and decoded by the device which sets the Write Enable Latch (WEL) to enable the PGPWD operation. The password can only be programmed before the Password Mode is selected by programming the Password Protection Mode bit to “0” in the ASP Register (ASP[2]). After the Password Protection Mode is selected the PGPWD command is ignored. The PGPWD command is entered by driving CE# low, followed by the instruction code and the password data bytes, least significant byte first, most significant bit of each byte first. The password is 64bits in length. CE# must be driven high after the 64th bit of data has been latched. If not, the PGPWD command is not executed. As soon as CE# is driven high, the PGPWD operation is initiated. While the PGPWD operation is in progress, the Status Register or Extended Read Register may be read to check the value of the Write In Progress (WIP) bit. The WIP bit is “1” during the PGPWD operation, and is “0” when it is completed. When the PGPWD operation is completed, the Write Enable Latch (WEL) is set to “0”. The maximum clock frequency for the PGPWD command is the same with Fast Read Operation. Figure 8.144 Program Password Sequence In SPI Mode Instruction = E8h CE # SCK SI SO 0 1 ... 7 8 9 ... 15 16 17 ... 23 ... 64 65 ... Mode 3 Mode 0 7 15 14 8 6 ... 0 63 62 56 ... ... ... 71 1 st byte Data In 2 nd byte Data In ... 8 th byte Data In High Impedence Figure 8.145 Program Password Sequence In QPI Mode E8h CE# SCK IO[3:0] 0 1 Mode 3 Mode 0 2 3 4 5 1 st byte Data In 2 nd byte Data In ... 8 th byte Data In ... 16 17 |
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