IS25LP256D-RHLA3-TR datasheet(158/179 Pages) ISSI

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IS25LP256D

IS25WP256D

Integrated Silicon Solution, Inc.- www.issi.com

158

Rev A15

08/05/2024

8.60 SET FREEZE BIT OPERATION (SFRZ, 91h)

The Set FREEZE Bit (SFRZ) command sets FREEZE (PPB Lock Register bit7) to one. Please refer to the section

6.6.3 PPB Lock Register for more detail. Before the SFRZ command can be accepted by the device, a Write Enable

(WREN) command must be issued and decoded by the device, which sets the Write Enable Latch (WEL) in the

Status Register to enable any write operations.

The SFRZ command is entered by driving CE# low, followed by the instruction code. CE# must be driven high after

the eighth bit of instruction has been latched in. If not, the SFRZ command is not executed. As soon as CE# is

driven high, the SFRZ operation is initiated. While the SFRZ operation is in progress, the Status Register or

Extended Read Register may still be read to check the value of the Write

In Progress (WIP) bit. The WIP bit is “1”

during the SFRZ operation, and is “0” when it is completed. When the SFRZ operation is completed, the WEL is

set to “0”. The maximum clock frequency for the SFRZ command is the same with Fast Read Operation.

Figure 8.140 Set FREEZE Bit Sequence In SPI Mode

Instruction = 91h

CE#

SCK

Mode 3

Mode 0

High Impedance

Figure 8.141 Set FREEZE Bit Sequence In QPI Mode

91h

CE#

SCK

IO[3:0]

Mode 3

Mode 0

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