LP8733-Q1 datasheet(25/86 Pages) TI2

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Enable

Time

Voltage

Resistive pull-down

(if enabled)

LDOx_VSET[4:0]

INT_LDO(LDOx_PG_INT)

nINT

Host clears

interrupts

Powergood

interrupts

Powergood

LDO_STAT(LDOx_PG_STAT)

Voltage decrease because of load

LDO_STAT(LDOx_STAT)

0 1

LDO_MASK(LDOx_PGF_MASK) = 0

LDO_MASK(LDOx_PGR_MASK) = 0

Figure 7-7. LDO Regulator Enable and Disable

The EN input pin has an integrated pulldown resistor. The pulldown resistor is controlled with the EN_PD bit in

the CONFIG register.

7.3.5.2 Changing Output Voltage

The output voltage of the regulator can be changed by writing to the BUCKx_VOUT and LDOx_VOUT register.

The voltage change for the buck regulator is always slew-rate controlled, and the slew-rate is defined by the

BUCKx_SLEW_RATE[2:0] bits in the BUCKx_CTRL_2 register. During voltage change, the forced PWM mode is

used automatically. If the dual-phase operation is forced by the BUCK0_FPWM_MP bit in the BUCK0_CTRL_1

phases are added and shedded automatically to follow the required slew rate. When the programmed output

voltage is achieved, the mode becomes the one defined by the load current, the BUCKx_FPWM bit in the

BUCKx_CTRL_1 register, and the BUCK0_FPWM_MP bit.

The voltage change and Power-Good interrupts are shown in Figure 7-8.

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LP8733-Q1

SNVSB64A – JUNE 2019 – REVISED JUNE 2021

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