7.2.2 Simplified Schematic Diagram of Each P-Port Input/Output

To Interrupt

Logic

P0−P7

VCC

GND

C

S

I

D

Q

FF

C

S

I

D

Q

FF

Write Pulse

Data From

Shift Register

Power-On

Reset

Read Pulse

Data to

Shift Register

100 µA

7.3 Feature Description

7.3.1 I2C Interface

I2C communication with this device is initiated by a commander sending a start condition, a high-to-low transition

on the SDA I/O while the SCL input is high. After the start condition, the device address byte is sent, most-

significant bit (MSB) first, including the data direction bit (R/ W). This device does not respond to the general call

address. After receiving the valid address byte, this device responds with an acknowledge, a low on the SDA

I/O during the high of the acknowledge-related clock pulse. The address inputs (A0–A2) of the responder device

must not be changed between the start and the stop conditions.

The data byte follows the address acknowledge. If the R/ W bit is high, the data from this device are the values

read from the P port. If the R/ W bit is low, the data are from the commander, to be output to the P port. The

data byte is followed by an acknowledge sent from this device. If other data bytes are sent from the commander,

following the acknowledge, they are ignored by this device. Data are output only if complete bytes are received

and acknowledged. The output data will be valid at time, tpv, after the low-to-high transition of SCL and during

the clock cycle for the acknowledge.

A stop condition, a low-to-high transition on the SDA I/O while the SCL input is high, is sent by the commander.

7.3.2 Interface Definition

BYTE

BIT

7 (MSB)

6

5

4

3

2

1

0 (LSB)

I2C responder

address

L

H

H

H

A2

A1

A0

R/ W

I/O data bus

P7

P6

P5

P4

P3

P2

P1

P0

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PCF8574A

SCPS069H – JULY 2001 – REVISED SEPTEMBER 2024

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