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PCM1753DBQ.B 数据表(PDF) 7 Page - Texas Instruments |
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PCM1753DBQ.B 数据表(HTML) 7 Page - Texas Instruments |
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7 / 41 page ![]() ML MC MD t (MDS) t (MCY) t (MDH) t (MCH) t (MLS) t (MCL) LSB t (MLH) t (MHH) S 3 256 f ´ 7 PCM1753, PCM1754, PCM1755 www.ti.com SLES092E – APRIL 2003 – REVISED JULY 2019 Product Folder Links: PCM1753 PCM1754 PCM1755 Submit Documentation Feedback Copyright © 2003–2019, Texas Instruments Incorporated (1) seconds (min); fS: sampling rate. (2) MC rising edge for LSB to ML rising edge. 7.8 Control Interface Timing Requirements these timing parameters are critical for proper control port operation MIN NOM MAX UNIT t(MCY) MC pulse cycle time See Figure 1. 100 ns t(MCL) MC low-level time 50 ns t(MCH) MC high-level time 50 ns t(MCH) ML high-level time See (1) ns t(MLS) ML falling edge to MC rising edge 20 ns t(MLH) ML hold time(2) 20 ns t(MDH) MD hold time 15 ns t(MCS) MD setup time 20 ns Figure 1. Control Interface Timing |
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