M41ST87WMX6TR datasheet(39/54 Pages) STMICROELECTRONICS

39 / 54 page

M41ST87W

Clock operation

DocID9497 Rev 11

39/54

powered-up periodically (at least once every few months) in order for this technique to be

beneficial. Additionally, if a battery low is indicated, data integrity should be verified upon

power-up via a checksum or other technique.

3.15

trec bit

Bit D7 of clock register 04h contains the trec bit (TR). trec refers to the automatic continuation

of the deselect time after VCC reaches VPFD. This allows for a voltage settling time before

WRITEs may again be performed to the device after a power-down condition. The trec bit

will allow the user to set the length of this deselect time as defined by Table 13: "trec

definitions".

Table 13: trec definitions

trec bit (TR)

STOP bit (ST)

trec time

Units

Min

Max

(1)

200

2000

µs

Notes:

(1)

Default setting.

3.16

Electronic serial number

The M41ST87Y/W has a unique 8-byte lasered serial number with parity. This serial

number is “read only” and is generated such that no two devices will contain an identical

number.

3.17

Oscillator stop detection

If the oscillator fail (OF) bit is internally set to a '1,' this indicates that the oscillator has

either stopped, or was stopped for some period of time, and can be used to judge the

validity of the clock and date data. This bit will be set to '1' any time the oscillator stops.

The following conditions can cause the OF bit to be set:

•

The first time power is applied (defaults to a '1' on power-up).

•

The voltage present on VCC or battery is insufficient to support oscillation.

•

The ST bit is set to '1.'

If the oscillator fail interrupt enable bit (OFIE) is set to a '1,' the

IRQ/OUTpinwillalsobe

asserted. The

IRQ/OUToutputisclearedbyresettingtheOFbitto'0,'resettingtheOFIE

bit to '0,' or if the

RSToutputisasserted(butisNOTclearedbyreadingtheflagregister).

The OF bit will remain set to '1' until written to logic '0.' The oscillator must start and have

run for at least 4 seconds before attempting to reset the OF bit to '0.' This function operates

both under normal power and in battery backup. If the trigger event occurs during a power-

down condition, this bit will be set correctly.

Note: The ABE bit must be set to '1' for the

IRQ/OUTpintobeactivatedinbatterybackup.

M41ST87WMX6TR 数据表(PDF) 39 Page - STMicroelectronics

M41ST87WMX6TR 数据表(HTML) 39 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54

数据表下载