Contents

M41ST87W

2/54

DocID9497 Rev 11

Contents

1

Description....................................................................................... 6

2

Operating modes ........................................................................... 12

2.1

2-wire bus characteristics................................................................ 13

2.1.1

Bus not busy..................................................................................... 13

2.1.2

Start data transfer............................................................................. 13

2.1.3

Stop data transfer ............................................................................. 13

2.1.4

Data valid.......................................................................................... 13

2.1.5

Acknowledge .................................................................................... 13

2.2

READ mode .................................................................................... 15

2.3

WRITE mode................................................................................... 17

2.4

Data retention mode........................................................................ 17

2.5

Tamper detection circuit .................................................................. 18

2.6

Tamper register bits (tamper 1 and tamper 2)................................. 18

2.6.1

Tamper enable bits (TEB1 and TEB2) ............................................. 18

2.6.2

Tamper bits (TB1 and TB2) .............................................................. 18

2.6.3

Tamper interrupt enable bits (TIE1 and TIE2).................................. 19

2.6.4

Tamper connect mode bit (TCM1 and TCM2) ................................. 19

2.6.5

Tamper polarity mode bits (TPM1 and TPM2) ................................. 19

2.6.6

Tamper detect sampling (TDS1 and TDS2) ..................................... 21

2.6.7

Tamper current high/tamper current low (TCHI/

������������������������������������������������1and

TCHI/

������������������������������������������������2)....................................................................................................21

2.6.8

RAM clear (CLR1 and CLR2) ........................................................... 21

2.6.9

RAM clear external (CLR1EXT and CLR2EXT) - available in SOX28

package only .................................................................................................... 21

2.7

Tamper detection operation ............................................................ 25

2.8

Sampling ......................................................................................... 25

2.9

Internal tamper pull-up/down current............................................... 26

2.10

Avoiding inadvertent tampers (normally closed configuration) ........ 26

2.11

Tamper event time-stamp ............................................................... 27

3

Clock operation ............................................................................. 28

3.1

Power-down time-stamp ................................................................. 28

3.2

TIMEKEEPER

® registers................................................................. 29

3.3

Calibrating the clock........................................................................ 31

3.4

Setting alarm clock registers ........................................................... 32

3.5

Watchdog timer ............................................................................... 34