Clock operation

M41T00S

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DocID10772 Rev 7

In the event the OF bit is found to be set to '1' at any time other than the initial power-up, the

STOP bit (ST) should be written to a '1,' then immediately reset to '0.' This will restart the

oscillator.

The following conditions can cause the OF bit to be set:

•

The first time power is applied (defaults to a '1' on power-up).

•

The voltage present on VCC is insufficient to support oscillation.

•

The ST bit is set to '1.'

•

External interference of the crystal.

The OF bit will remain set to '1' until written to logic '0.' The oscillator must start and have run

for at least 4 seconds before attempting to reset the OF Bit to '0.'

3.2.3

Output driver pin

When the FT bit is not set, the FT/OUT pin becomes an output driver that reflects the

contents of D7 of the calibration register. In other words, when D7 (OUT bit) and D6 (FT bit)

of address location 07h are a '0,' then the FT/OUT pin will be driven low.

Note:

The FT/OUT pin is an open drain which requires an external pull-up resistor.

3.2.4

Preferred initial power-on default

Upon initial application of power to the device, the ST and FT bits are set to a '0' state, and

the OF and OUT bits will be set to a '1.' All other register bits will initially power-on in a

random state (see Table 4).

Table 3. FT/OUT pin status

Power mode

(FT) D6 of 07h

(OUT bit) D7 of 07h

Status

VCC Mode

0

0

Low

0

1

High

1

1 or 0

Frequency Test

Battery Mode

N.A.

N.A.

High

Table 4. Preferred default values

Condition

ST

Out

FT

OF

Initial power-up(1)

1. State of other control bits undefined.

0

1

0

1

Subsequent power-up (with battery backup)(2)

2. UC = Unchanged

UC

UC

0

UC