M41ST87YSS6F datasheet(22/54 Pages) STMICROELECTRONICS

22 / 54 page

Operating modes

M41ST87W

22/54

DocID9497 Rev 11

from being pulled to ground by the output of the charge pump when it is in shut-down mode

(

SHDN=logiclow).ThegatesofbothMOSFETsshouldbeconnectedtoTP

CLR as shown

in Figure 20: "RAM clear hardware hookup (SOX28 package only)". One n-channel

enhancement MOSFET should be placed between the output of the inverting charge pump

and the VOUT of the M41ST87. The other MOSFET should be an enhancement mode p-

channel, and placed between VOUT of the M41ST87 and VCC of the external SRAM. When

TPCLR goes high after a tamper condition occurs, the n-channel MOSFET will turn on and

the p-channel will turn off. During normal operating conditions, TPCLR will be low and the p-

channel will be on, while the n-channel will be off.

Table 5: Tamper detection current (normally closed - TCMX = '0')

TDSX

TCHI/

��X

Tamper circuit mode

Current at 3.0 V (typ)

(1)(2)

Unit

Continuous monitoring / 10 MW pull-up/-down

0.3

µA

Continuous monitoring / 1 MW pull-up/-down

3.0

µA

Sampling (1 Hz) / 10 MW pull-up/-down

0.3

Sampling (1 Hz) / 1 MW pull-up/-down

3.0

Notes:

(1)

Per tamper detect input

(2)

When calculating battery lifetime, this current should be added to IBAT current listed in Table 19: "DC characteristics".

Figure 17: Tamper detect sampling options

TAMPER LO,

NORMALLY OPEN

TAMPER HI,

NORMALLY CLOSED

User

Configuration

TDS

X = 0

TDS

X = 1

TDS

X = 0

TDS

X = 1

TAMPER HI,

NORMALLY OPEN

TAMPER LO,

NORMALLY, CLOSED

CONTINUOUS

MONITORING

CONTINUOUS

MONITORING

CONTINUOUS

MONITORING

SAMPLED

MONITORING

CONTINUOUS

MONITORING

SAMPLED

MONITORING

VCC (VOUT)

TCM

X, TPMX

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