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L99LD01 数据表(PDF) 35 Page - STMicroelectronics |
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L99LD01 数据表(HTML) 35 Page - STMicroelectronics |
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35 / 69 page ![]() DocID025319 Rev 3 35/69 L99LD01 SPI functional description 68 During the same sequence outgoing data are shifted out MSB first on the falling edge of the CSN pin and subsequent bits on the falling edge of the serial clock (SCK). The first byte corresponds to the Global Status Byte and the second to the previous content of the addressed register. Figure 23. SPI write operation Read mode The read mode of the device allows to read and to check the state of any register. Incoming data are sampled on the rising edge of the serial clock (SCK), MSB first. Outgoing data are shifted out MSB first on the falling edge of the CSN pin and others on the falling edge of the serial clock (SCK). The first byte corresponds to the Global Status Byte and the second to the content of the addressed register. In case of a read mode on an unused address, the ‘global status/error’ byte on the SDO pin is following by 00H byte. In order to avoid inconsistency between the Global status byte and the status register, the status register contents are frozen during SPI communication. Figure 24. SPI read operation Read and clear status command The read and clear status operation is used to clear the content of the addressed status register (see Section : Status registers 1). A read and clear status operation with address CSN SDO SDI 0MSB MSB MSB LSB LSB LSB LSB Command Byte Global Status Byte (8 bit) Data (previous content of register) Data (8 bit) 0 Address MSB CSN SDO SDI MSB MSB MSB LSB LSB LSB Command Byte Global Status Byte (8 bit) Data (8 bit) Don’t care (8 bit) 0LSB 1 Address MSB |
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