ICS345

TRIPLE PLL FIELD PROGRAMMABLE SS VERSACLOCK SYNTHESIZER

EPROM CLOCK SYNTHESIZER

IDT™ / ICS™ TRIPLE PLL FIELD PROGRAMMABLE SS VERSACLOCK SYNTHESIZER 6

ICS345

REV K 110207

AC Electrical Characteristics

Unless stated otherwise, VDD = 3.3 V ±5%, Ambient Temperature -40 to +85

° C

Note 1: Measured with 15 pF load.

Note 2: Duty Cycle is configuration dependent. Most configurations are min 45% / max 55%

Note 3: IDT test mode output occurs for first 170 clock cycles on CLK7 for each PLL powered up. PDTS transition

high on select address change.

Note 4: The actual ppm error will be displayed in the VersaClock software when the programming file is generated

for the customer’s specific configuration. In general, zero ppm error can be achieved, but please note that the

device cannot improve upon the error of the input reference clock. For example, if the input crystal has 25 ppm error,

then the outputs will also have 25 ppm error.

Thermal Characteristics

Parameter

Symbol

Conditions

Min.

Typ.

Max.

Units

Input Frequency

Fundamental crystal

5

27

MHz

Input clock

2

50

MHz

Output Frequency

VDD=3.3 V

0.25

200

MHz

Output Rise Time

20% to 80%, Note 1

1

ns

Output Fall Time

80% to 20%, Note 1

1

ns

Duty Cycle

Note 2

40

49-51

60

%

Output Frequency Synthesis

Error (Note 4)

Configuration Dependent

0

ppm

Power-up Time

PLL lock-time from

power-up, Note 3

410

ms

PDTS goes high until stable

CLK output, Spread

Spectrum Off, Note 3

0.2

2

ms

PDTS goes high until stable

CLK output, Spread

Spectrum On, Note 3

47

ms

One Sigma Clock Period Jitter

Configuration Dependent

50

ps

Maximum Absolute Jitter

Deviation from Mean.

Configuration Dependent

+200

ps

Pin-to-Pin Skew

Low Skew Outputs

-250

250

ps

Parameter

Symbol

Conditions

Min.

Typ.

Max.

Units

Thermal Resistance Junction to

Ambient

Still air

135

° C/W

1 m/s air flow

93

° C/W

3 m/s air flow

78

° C/W

Thermal Resistance Junction to Case

60

° C/W