Vcc

Unused Input

Input

Output

Input

Unused Input

Output

Supply Voltage (VCC) [V]

1.8

2

2.2

2.4

2.6

2.8

3

3.2

3.4

2.4

2.6

2.8

3

3.2

3.4

3.6

3.8

4

4.2

D001

13

SN54LVC04A, SN74LVC04A

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SCAS281T – JANUARY 1993 – REVISED NOVEMBER 2016

Product Folder Links: SN54LVC04A SN74LVC04A

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Copyright © 1993–2016, Texas Instruments Incorporated

Typical Application (continued)

9.2.3 Application Curves

Figure 4. Typical Application Curve

10 Power Supply Recommendations

The power supply can be any voltage between the minimum and maximum supply voltage rating located in the

Recommended Operating Conditions.

Each VCC pin must have a good bypass capacitor to prevent power disturbance. For devices with a single supply,

0.1 µF is recommended. If there are multiple VCC pins, 0.01 µF or 0.022 µF is recommended for each power pin.

It is acceptable to parallel multiple bypass caps to reject different frequencies of noise. A 0.1 µF and 1 µF are

commonly used in parallel. The bypass capacitor must be installed as close to the power pin as possible for best

results.

11 Layout

11.1 Layout Guidelines

When using multiple bit logic devices, inputs must not float. In many cases, functions or parts of functions of

digital logic devices are unused. Some examples are when only two inputs of a triple-input AND gate are used,

or when only 3 of the 4-buffer gates are used. Such input pins must not be left unconnected because the

undefined voltages at the outside connections result in undefined operational states.

Specified in Figure 5 are rules that must be observed under all circumstances. All unused inputs of digital logic

devices must be connected to a high or low bias to prevent them from floating. The logic level that must be

applied to any particular unused input depends on the function of the device. Generally they are tied to GND or

VCC, whichever makes more sense or is more convenient. It is acceptable to float outputs unless the part is a

transceiver. If the transceiver has an output enable pin, it disables the outputs section of the part when asserted.

This does not disable the input section of the I/Os so they also cannot float when disabled.

11.2 Layout Example

Figure 5. Layout Diagram