PM8805 datasheet(39/45 Pages) STMICROELECTRONICS

39 / 45 page

DS12813 Rev 1

39/45

PM8805

Layout guidelines

Here follows a list of recommended procedures to be considered during the routing of a

board layout.

The basic assumption is using a 4 layer, 35 um Cu thickness board layout.

The top layer should be used for the exposed pads and for most of the signal routing.

The bottom layer is used mainly for replicated, enlarged copper areas of top exp pads and

for remaining signal not routed on top.

Inner layers is for GND copper plane and for routing of VOB and VOUT signals.

In more detail:

The layout must comply with the minimum creepage distance of 0.7 mm between high-

voltage pins and adjacent low-voltage pins. Take into account that this requirement is valid

for top and bottom layers where the copper areas and/or traces are exposed (uncoated

PCB), while for inner layers the creepage distance can be reduced to about 0.2 mm.

Use short traces of at least 30 mils to connect the data transformer to the signals: IN12,

IN36, IN45 and IN78; those signals may carry up to 1 A each trace. The trace of those

signals may have an impact on the current unbalance at PD interface: try to route those

signals with the same trace width and same length. Route those signals in inner layers

and replicate exposed pad copper area on the bottom layers, connecting them with 4 -

6 vias for a strong electrical and thermal path: the equivalent copper area for each

signal should be around 0.12"x0.12" minimum (3 x 3 mm repeated at least 3 times);

better results are obtained with copper areas of 0.2"x0.2" (5x5 mm).

The 4 copper areas at each corner of the package is connected to the other layers with

the same copper area using multiple vias, at least 4-6 for each area on top layer.

AGND signal must be connected to GND copper plane with a short trace of 20 mils

minimum.

VOB large exp pad must be connected with the exp pad of the hot swap MOSFET and

both connected to a large VOB copper area in an inner layer and on the bottom layer

with 4 - 6 vias close to each MOSFET die position for a strong electrical and thermal

path: the equivalent copper area for VOB signal should be around 0.6"x0.8" (15 x 20

mm repeated at least 2 times plus the min. pad shape repeated again two times).

VOUT signal may carry up to 2 A; it is connected to an inner copper plane with short

trace and at least 4-6 vias. In case it is routed with a short trace to the load, use a trace

width of 60 mils.

5.Remaining signals is routed on top and bottom layer, with no special care except wtth

respect to the creepage distances toward the other signals.

Figure 13 shows an example of a real layout done on a 4 layer PCB.

PM8805 数据表(PDF) 39 Page - STMicroelectronics

PM8805 数据表(HTML) 39 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45

数据表下载