3

1

6

In2

In1

In0

4

Y

SN74LVC1G98

SCES417L – DECEMBER 2002 – REVISED DECEMBER 2013

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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

Function Table

INPUTS

OUTPUT

Y

In2

In1

In0

L

L

L

H

L

L

H

H

L

H

L

L

L

H

H

L

H

L

L

H

H

L

H

L

H

H

L

H

H

H

H

L

Logic Diagram (Positive Logic)

Function Selection Table

LOGIC FUNCTION

FIGURE NO.

2-to-1 data selector with inverted output

Figure 1

2-input NAND gate

Figure 2

2-input NOR gate with one inverted input

Figure 3

2-input AND gate with one inverted input

Figure 3

2-input NAND gate with one inverted input

Figure 4

2-input OR gate with one inverted input

Figure 4

2-input NOR gate

Figure 5

Noninverted buffer

Figure 6

Inverter

Figure 7

2

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