8.2.2.2.1 Enable Times

Calculate the enable times for the SN74LVC1T45 using the following formulas:

• tPZH (DIR to A) = tPLZ (DIR to B) + tPLH (B to A)

• tPZL (DIR to A) = tPHZ (DIR to B) + tPHL (B to A)

• tPZH (DIR to B) = tPLZ (DIR to A) + tPLH (A to B)

• tPZL (DIR to B) = tPHZ (DIR to A) + tPHL (A to B)

In a bidirectional application, these enable times provide the maximum delay from the time the DIR bit is

switched until an output is expected. For example, if the SN74LVC1T45 initially is transmitting from A to B, then

the DIR bit is switched; the B port of the device must be disabled before presenting it with an input. After the

B port has been disabled, an input signal applied to it appears on the corresponding A port after the specified

propagation delay.

8.2.2.3 Application Curve

Figure 8-4. Translation Down (5V to 1.8V) at 2.5 MHz

8.3 Power Supply Recommendations

Always apply a ground reference to the GND pins first. This device is designed for glitch free power sequencing

without any supply sequencing requirements such as ramp order or ramp rate.

This device was designed with various power supply sequencing methods in mind to help prevent unintended

triggering of downstream devices, as described in Glitch-free Power Supply Sequencing.

8.4 Layout

8.4.1 Layout Guidelines

To ensure reliability of the device, the following common printed-circuit board layout guidelines are

recommended:

• Bypass capacitors should be used on power supplies.

• Short trace lengths should be used to avoid excessive loading.

• Placing pads on the signal paths for loading capacitors or pullup resistors to help adjust rise and fall times of

signals depends on the system requirements

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SN74LVC1T45

SCES515N – DECEMBER 2003 – REVISED JUNE 2024

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