ICS844002I-01

FEMTOCLOCKS™ CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER

IDT™ / ICS™ LVDS FREQUENCY SYNTHESIZER

2

ICS844002AGI-01 REV. C SEPTEMBER 28, 2007

Table 1. Pin Descriptions

NOTE: Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.

Table 2. Pin Characteristics

Number

Name

Type

Description

1, 7

nc

Unused

No connect.

2, 20

Power

Output supply pins.

3, 4

Q0, Q0

Output

Differential output pair. LVDS interface levels.

5

MR

Input

Pulldown

Active HIGH Master Reset. When logic HIGH, the internal dividers are reset

causing the true outputs Qx to go low and the inverted outputs Qx to go high.

When logic LOW, the internal dividers and the outputs are enabled.

LVCMOS/LVTTL interface levels.

6

PLL_SEL

Input

Pulldown

Selects between the PLL and REF_CLK as input to the dividers. When LOW,

selects PLL (PLL Enable). When HIGH, deselects the reference clock (PLL

Bypass). LVCMOS/LVTTL interface levels.

Power

Analog supply pin.

9,

11

FSEL0,

F_SEL1

Input

Pulldown

Frequency select pins. LVCMOS/LVTTL interface levels.

10

Power

Core supply pins.

12,

13

XTAL_IN

Input

Parallel resonant crystal interface. XTAL_OUT is the output,

XTAL_IN is the input.

14

REF_CLK

Input

Pulldown

Non-inverting differential clock input.

15

XTAL_SEL

Input

Pulldown

Selects between crystal or REF_CLK inputs as the PLL Reference source.

Selects XTAL inputs when LOW. Selects REF_CLK when HIGH.

LVCMOS/LVTTL interface levels.

16

nc

Unused

No connect.

17

GND

Power

Power supply ground.

18, 19

Q1, Q1

Output

Differential output pair. LVDS interface levels.

Symbol

Parameter

Test Conditions

Minimum

Typical

Maximum

Units

Input Capacitance

4

pF

51

k

Ω