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HCS360-I/P 数据表(PDF) 13 Page - Microchip Technology |
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HCS360-I/P 数据表(HTML) 13 Page - Microchip Technology |
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13 / 28 page ![]() 2001 Microchip Technology Inc. DS40152D-page 13 HCS360 5.0 SPECIAL FEATURES 5.1 Code Word Completion Code word completion is an automatic feature that ensures that the entire code word is transmitted, even if the button is released before the transmission is com- plete and that a minimum of two words are completed. The HCS360 encoder powers itself up when a button is pushed and powers itself down after two complete words are transmitted if the user has already released the button. If the button is held down beyond the time for one transmission, then multiple transmissions will result. If another button is activated during a transmission, the active transmission will be aborted and the new code will be generated using the new button information. 5.2 Long Guard Time Federal Communications Commission (FCC) part 15 rules specify the limits on fundamental power and harmonics that can be transmitted. Power is calculated on the worst case average power transmitted in a 100ms window. It is therefore advantageous to minimize the duty cycle of the transmitted word. This can be achieved by minimizing the duty cycle of the individual bits and by extending the guard time between transmissions. long guard time (LNGRD) is used for reducing the average power of a transmission. This is a selectable feature. Using the LNGRD allows the user to transmit a higher amplitude transmission if the transmission time per 100 ms is shorter. The FCC puts constraints on the average power that can be transmitted by a device, and LNGRD effectively prevents continuous transmission by only allowing the transmission of every second word. This reduces the average power transmitted and hence, assists in FCC approval of a transmitter device. 5.3 CRC (Cycle Redundancy Check) Bits The CRC bits are calculated on the 65 previously trans- mitted bits. The CRC bits can be used by the receiver to check the data integrity before processing starts. The CRC can detect all single bit and 66% of double bit errors. The CRC is computed as follows: EQUATION 5-1: CRC CALCULATION and with and Din the nth transmission bit 0 ≤ n ≤ 64 5.4 Secure Learning In order to increase the level of security in a system, it is possible for the receiver to implement what is known as a secure learning function. This can be done by utilizing the seed value on the HCS360 which is stored in EEPROM. Instead of the normal key generation method being used to create the encryption key, this seed value is used and there should not be any mathematical rela- tionship between serial numbers and seeds for the best security. Note: The CRC may be wrong when the battery voltage is around either of the VLOW trip points. This may happen because VLOW is sampled twice each transmission, once for the CRC calculation (PWM is low) and once when VLOW is transmitted (PWM is high). VDD tends to move slightly during a transmis- sion which could lead to a different value for VLOW being used for the CRC calculation and the transmission . Work around: If the CRC calculation is incor- rect, recalculate for the opposite value of VLOW. CRC 1 [] n 1 + CRC 0 [] n Di n ∧ = CRC 0 [] n 1 + CRC 0 [] n Di n ∧ () CRC 1 [] n ∧ = CRC 10 , [] 0 0 = |
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