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TAS2505IRGET 数据表(PDF) 7 Page - Texas Instruments

部件名 TAS2505IRGET
功能描述  TAS2505 2.6W Digital/Analog Input Class-D Speaker Amplifier With Audio Processing
PDF  36 Pages
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制造商  TI2 [Texas Instruments]
网页  https://www.ti.com
标志 TI2 - Texas Instruments

TAS2505IRGET 数据表(HTML) 7 Page - Texas Instruments

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All specifications at 25°C, DVDD = 1.8V(1)
PARAMETER
IOVDD = 1.8V
IOVDD = 3.3V
UNIT
MIN
MAX
MIN
MAX
ts(DI)
DIN setup
8
6
ns
th(DI)
DIN hold
8
6
ns
tr
Rise time
25
10
ns
tf
Fall time
25
10
ns
(1)
ll timing specifications are measured at characterization but not tested at final test.
5.7 I2S/LJF/RJF Timing in Slave Mode
All specifications at 25°C, DVDD = 1.8V(1)
PARAMETER
IOVDD = 1.8V
IOVDD = 3.3V
UNIT
MIN
MAX
MIN
MAX
tH(BCLK)
BCLK high period
35
35
ns
tL(BCLK)
BCLK low period
35
35
ns
ts(WS)
WCLK setup
8
6
ns
th(WS)
WCLK hold
8
6
ns
ts(DI)
DIN setup
8
6
ns
th(DI)
DIN hold
8
6
ns
tr
Rise time
4
4
ns
tf
Fall time
4
4
ns
(1)
All timing specifications are measured at characterization but not tested at final test.
5.8 DSP Timing in Master Mode
All specifications at 25°C, DVDD = 1.8V(1)
PARAMETER
IOVDD = 1.8V
IOVDD = 3.3V
UNIT
MIN
MAX
MIN
MAX
td(WS)
WCLK delay
45
45
ns
ts(DI)
DIN setup
8
6
ns
th(DI)
DIN hold
8
6
ns
tr
Rise time
25
10
ns
tf
Fall time
25
10
ns
(1)
All timing specifications are measured at characterization but not tested at final test.
5.9 DSP Timing in Slave Mode
All specifications at 25°C, DVDD = 1.8V(1)
PARAMETER
IOVDD = 1.8V
IOVDD = 3.3V
UNIT
MIN
MAX
MIN
MAX
tH(BCLK)
BCLK high period
35
35
ns
tL(BCLK)
BCLK low period
35
35
ns
ts(WS)
WCLK setup
8
8
ns
th(WS)
WCLK hold
8
8
ns
ts(DI)
DIN setup
8
8
ns
th(DI)
DIN hold
8
8
ns
tr
Rise time
4
4
ns
tf
Fall time
4
4
ns
(1)
All timing specifications are measured at characterization but not tested at final test.
www.ti.com
TAS2505
SLAS778D – FEBRUARY 2013 – REVISED JANUARY 2025
Copyright © 2025 Texas Instruments Incorporated
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Product Folder Links: TAS2505



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