9.1.5 Operating the Power-Down Feature

The power-down feature on the THP210 puts the device into a low power-consumption state, with quiescent

current minimized. To force the device into the low-power state, drive the PD pin lower than the power-down

threshold voltage (VVS+ – 2 V). Driving the PD pin lower than the power-down threshold voltage forces the

internal logic to disable both the differential and common-mode amplifiers. The PD pin has an internal pullup

current that allows the pin to be used in an open-drain MOSFET configuration without an additional pullup

resistor, as seen in Figure 9-7. In this configuration, the logic level can be referenced to the MOSFET, and the

voltage at the PD pin is level-shifted to account for use with high supply voltages. Be sure to select an N-type

MOSFET with a maximum BVDSS greater than the total supply voltage.

PD

1 µA

To

amplifier

core

VS+

GND

THP210

Enabled

MOSFET

THRESHOLD

Powerdown

Figure 9-7. Power-Down ( PD) Pin Interface With Low-Voltage Logic Level Signals

For applications that do not use the power-down feature, tie the PD pin to the positive supply voltage.

When PD is low (device is in power down) the output pins is in a high-impedance state.

9.1.6 Driving Capacitive Loads

In most ADC applications, an FDA is required to drive capacitive load of an RC charge kickback filter. Other

applications may require some other next-stage devices to be driven. The strong output stage of the THP210

drives higher capacitive loads compared to other FDAs. Figure 6-25 implies that the small-signal overshoot

is less then 20% at a direct capacitive load connection of 140 pF. To help avoid instability and drive higher

capacitive loads, add a small resistor (referred to as isolation resistor RISO in both this plot and Figure 6-26) at

the outputs of the THP210 before the capacitive load.

THP210

SBOS932C – JANUARY 2020 – REVISED MARCH 2021

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