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TLC5926IPWPR 数据表(PDF) 7 Page - Texas Instruments

部件名 TLC5926IPWPR
功能描述  TLC592x 16-Channel Constant-Current LED Sink Drivers
PDF  39 Pages
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制造商  TI2 [Texas Instruments]
网页  https://www.ti.com
标志 TI2 - Texas Instruments

TLC5926IPWPR 数据表(HTML) 7 Page - Texas Instruments

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TLC5926, TLC5927
www.ti.com
SLVS677C – JULY 2008 – REVISED OCTOBER 2015
7.7 Timing Recommendations
VDD = 3 V to 5.5 V (unless otherwise noted)
MIN
MAX
UNIT
tw(L)
LE(ED1) pulse duration
Normal mode
20
ns
tw(CLK)
CLK pulse duration
Normal mode
20
ns
tw(OE)
OE(ED2) pulse duration
Normal mode
1000
ns
tsu(D)
Setup time for SDI
Normal mode
7
ns
th(D)
Hold time for SDI
Normal mode
3
ns
tsu(L)
Setup time for LE(ED1)
Normal mode
18
ns
th(L)
Hold time for LE(ED1)
Normal mode
18
ns
tw(CLK)
CLK pulse duration
Error Detection mode
20
ns
tw(ED2)
OE(ED2) pulse duration
Error Detection mode
2000
ns
tsu(ED1)
Setup time for LE(ED1)
Error Detection mode
7
ns
th(ED1)
Hold time for LE(ED1)
Error Detection mode
10
ns
tsu(ED2)
Setup time for OE(ED2)
Error Detection mode
7
ns
th(ED2)
Hold time for OE(ED2)
Error Detection mode
10
ns
fCLK
Clock frequency
Cascade operation, VDD = 3 V to 5.5 V
30
MHz
7.8 Switching Characteristics: VDD = 3 V
VDD = 3 V, TJ = –40°C to 125°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
tPLH1
Low-to-high propagation delay time, CLK to OUTn
35
65
105
ns
tPLH2
Low-to-high propagation delay time, LE(ED1) to OUTn
35
65
105
ns
tPLH3
Low-to-high propagation delay time, OE(ED2) to OUTn
35
65
105
ns
tPLH4
Low-to-high propagation delay time, CLK to SDO
20
45
ns
tPHL1
High-to-low propagation delay time, CLK to OUTn
200
300
470
ns
tPHL2
High-to-low propagation delay time, LE(ED1) to OUTn
200
300
470
ns
tPHL3
High-to-low propagation delay time, OE(ED2) to OUTn
200
300
470
ns
tPHL4
High-to-low propagation delay time, CLK to SDO
20
40
ns
tw(CLK)
Pulse duration, CLK
20
ns
VIH = VDD, VIL = GND,
tw(L)
Pulse duration LE(ED1)
20
ns
Rext = 360 Ω, VL = 4 V,
tw(OE)
Pulse duration, OE(ED2)
1000
ns
RL = 44 Ω, CL = 70 pF,
tw(ED2)
Pulse duration, OE(ED2) in Error Detection mode
2
μs
CG = 0.992
th(ED1,ED2)
Hold time, LE(ED1), and OE(ED2)
10
ns
th(D)
Hold time, SDI
5
ns
tsu(D,ED1,ED2) Setup time, SDI, LE(ED1), and OE(ED2)
7
ns
th(L)
Hold time, LE(ED1), Normal mode
18
ns
tsu(L)
Setup time, LE(ED1), Normal mode
18
ns
tr
Rise time, CLK (1)
500
ns
tf
Fall time, CLK (1)
500
ns
tor
Rise time, outputs (off)
245
ns
tof
Rise time, outputs (on)
600
ns
fCLK
Clock frequency
Cascade operation
30
MHz
(1)
If the devices are connected in cascade and tr or tf is large, it may be critical to achieve the timing required for data transfer between two
cascaded devices.
Copyright © 2008–2015, Texas Instruments Incorporated
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Product Folder Links: TLC5926 TLC5927



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