LOAD

ISO

o

ISO

LOAD

1 + C

× R

× s

T(s) =

1 + R + R

× C

× s

CLOAD

+

±

VIN

VOUT

+VS

RISO

-VS

Copyright © 2016, Texas Instruments Incorporated

21

TLV170, TLV2170, TLV4170

www.ti.com

SBOS782A – NOVEMBER 2016 – REVISED MAY 2018

Product Folder Links: TLV170 TLV2170 TLV4170

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Copyright © 2016–2018, Texas Instruments Incorporated

8 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

8.1 Application Information

The TLVx170 family of op amps provides high overall performance in a large number of general-purpose

applications. As with all amplifiers, applications with noisy or high-impedance power supplies require decoupling

capacitors placed close to the device pins. In most cases, 0.1-µF capacitors are adequate. Follow the additional

recommendations in the Layout Guidelines section in order to achieve the maximum performance from this

device. Many applications can introduce capacitive loading to the output of the amplifier (potentially causing

instability). One method of stabilizing the amplifier in such applications is to add an isolation resistor between the

amplifier output and the capacitive load. The design process for selecting this resistor is given in the Typical

Application section.

8.2 Typical Application

This circuit can be used to drive capacitive loads (such as cable shields, reference buffers, MOSFET gates, and

diodes). The circuit uses an isolation resistor (RISO) to stabilize the output of an op amp. RISO modifies the open-

loop gain of the system to ensure the circuit has sufficient phase margin.

Figure 30. Unity-Gain Buffer With RISO Stability Compensation

8.2.1 Design Requirements

The design requirements are:

•

Supply voltage: 30 V (±15 V)

•

Capacitive loads: 100 pF, 1000 pF, 0.01 μF, 0.1 μF, and 1 μF

•

Phase margin: 45° and 60°

8.2.2 Detailed Design Procedure

Figure 30 shows a unity-gain buffer driving a capacitive load. Equation 1 shows the transfer function for the

circuit in Figure 30. Not shown in Figure 30 is the open-loop output resistance of the op amp, Ro.

(1)

The transfer function in Equation 1 has a pole and a zero. The frequency of the pole (fp) is determined by (Ro +

RISO) and CLOAD. Components RISO and CLOAD determine the frequency of the zero (fz). A stable system is

obtained by selecting RISO such that the rate of closure (ROC) between the open-loop gain (AOL) and 1/β is

20 dB per decade; see Figure 31. The 1/β curve for a unity-gain buffer is 0 dB.