LOGIC DIAGRAMS (continued)

40102B

TRUTH TABLE

Control Inputs

CLR

APE

SPE

CI / CE

Preset Mode

Action

1

1

1

1

Inhibit Counter

1

1

1

0

Count Down

11

0

X

Synchronous

Preset on Next Positive Clock Transition

1

0

X

X

Preset Asynchrounously

0X

X

X

Asynchronous

Clear to Maximum Count

Timing Diagram for 40102B and 40103B

Notes :

1. 0 = Low level

1 = High level

X = Don’t care

2. Clock connected to clock input.

3. Synchronous operation : changes occur on negative-to-positive clock transitions..

JAM inputs : HCC/HCF010B ; MSD = J7, J6, J5, J4 (J7 is MSB)

LSD = J3, J2, J1, J0 (J3 is MSB)

HCC/HCF40103B Binary ; MSB = J7, LSB = J0

HCC/HCF40102B/40103B

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