AD3530R datasheet(42/49 Pages) AD

42 / 49 page

Data Sheet

AD3530/AD3530R

analog.com

Rev. A | 42 of 49

STATUS CONTROL REGISTER

Address: 0xC2, Reset: 0x04, Name: STATUS_CONTROL

Event flags due to start up sequence, interface, reset, and update can be read. Write 1 to clear.

[7:4] RESERVED

[0] RESERVED

[3] UPDATE_ERR (R/W1C)

[1] INTERFACE_ERR (R/W1C)

[2] RESET_WARNING (R/W1C)

Table 31. Bit Descriptions for STATUS_CONTROL

Bits

Bit Name

Description

Reset

Access

[7:4]

RESERVED

Reserved.

0x0

UPDATE_ERR

Update Error. Status to indicate that there was an attempt to update a DAC_CHn within 640ns since

the last update

0x0

R/W1C

0: Error 0. All updates successful.

1: Error 1. Overlapping updates attempted.

RESET_WARNING

Reset Warning. Status to indicate if the device went through a reset event.

0x1

R/W1C

0: Warning 0. Reset warning flag cleared.

1: Warning 1. Reset event occurred.

INTERFACE_ERR

Interface Error. Status to indicate an error flag is asserted in INTERFACE_STATUS_A.

0x0

R/W1C

0: Error 0. No interface error.

1: Error 1. Interface error.

RESERVED

Reserved.

0x0

HARDWARE LDAC ENABLE 0 REGISTER

Address: 0xD0, Reset: 0xFF, Name: HW_LDAC_EN_0

Enable hardware LDAC functionality for channel 0 to channel 7

[7] HLD_EN_CH_7 (R/W)

[0] HLD_EN_CH_0 (R/W)

[6] HLD_EN_CH_6 (R/W)

[1] HLD_EN_CH_1 (R/W)

[5] HLD_EN_CH_5 (R/W)

[2] HLD_EN_CH_2 (R/W)

[4] HLD_EN_CH_4 (R/W)

[3] HLD_EN_CH_3 (R/W)

Table 32. Bit Descriptions for HW_LDAC_EN_0

Bits

Bit Name

Description

Reset

Access

HLD_EN_CH_7

Hardware LDAC Enable Channel 7. Enable/disable hardware LDAC functionality on Channel 7.

0x1

R/W

0: HLD En 0. Disable hardware LDAC on Channel 7.

1: HLD En 1. Enable hardware LDAC on Channel 7.

HLD_EN_CH_6

Hardware LDAC Enable Channel 6. Enable/disable hardware LDAC functionality on Channel 6.

0x1

R/W

0: HLD En 0. Disable hardware LDAC on Channel 6.

1: HLD En 1. Enable hardware LDAC on Channel 6.

HLD_EN_CH_5

Hardware LDAC Enable Channel 5. Enable/disable hardware LDAC functionality on Channel 5.

0x1

R/W

0: HLD En 0. Disable hardware LDAC on Channel 5.

1: HLD En 1. Enable hardware LDAC on Channel 5.

HLD_EN_CH_4

Hardware LDAC Enable Channel 4. Enable/disable hardware LDAC functionality on Channel 4.

0x1

R/W

0: HLD En 0. Disable hardware LDAC on Channel 4.

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