MAX809, MAX810

4

APPLICATIONS INFORMATION

VCC Transient Rejection

reset

timing

during

power–up,

power–down,

and

brownout/sag conditions, and rejects negative–going

transients (glitches) on the power supply line. Figure 1

shows the maximum transient duration vs. maximum

negative excursion (overdrive) for glitch rejection. Any

combination of duration and overdrive which lies under the

curve will not generate a reset signal. Combinations above

the curve are detected as a brownout or power–down.

Transient immunity can be improved by adding a capacitor

Figure 1. Maximum Transient Duration vs. Overdrive

for Glitch Rejection at 25

° C

Duration

VTH

Overdrive

VCC

TA = +25° C

MAX8xxL/M/J

1

10

100

1000

0

90

160

240

320

400

RESET COMPARATOR OVERDRIVE,

(VTH – VCC (mV)

MAX8xxR/S/T

RESET Signal Integrity During Power–Down

Below this voltage the output becomes an ”open circuit” and

does not sink current. This means CMOS logic inputs to the

µP will be floating at an undetermined voltage. Most digital

systems are completely shutdown well above this voltage.

However, in situations where RESET must be maintained

from RESET to ground to discharge stray capacitances and

hold the output low (Figure 2). This resistor value, though

not critical, should be chosen such that it does not

appreciably load RESET under normal operation (100k

W

will be suitable for most applications). Similarly, a pull–up

VCC

VCC

RESET

R1

100 k

MAX809

GND

Figure 2. Ensuring RESET Valid to VCC = 0 V

Processors With Bidirectional I/O Pins

Some

µP’s (such as Motorola 68HC11) have

bi–directional reset pins. Depending on the current drive

capability of the processor pin, an indeterminate logic level

may result if there is a logic conflict. This can be avoided

by adding a 4.7k

W resistor in series with the output of the

MAX809/810 (Figure 3). If there are other components in

the system which require a reset signal, they should be

buffered so as not to load the reset line.

If the other

components are required to follow the reset I/O of the

µP, the

buffer should be connected as shown with the solid line.

VCC

VCC

mP

RESET

MAX809

GND

GND

47 k

Figure 3. Interfacing to Bidirectional Reset I/O

RESET

VCC

BUFFERED RESET

TO OTHER SYSTEM

COMPONENTS

BUFFER

MAX809, MAX810