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IS25LEG-RGLA2:P-TR 数据表(PDF) 174 Page - Integrated Silicon Solution, Inc |
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IS25LEG-RGLA2:P-TR 数据表(HTML) 174 Page - Integrated Silicon Solution, Inc |
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174 / 193 page ![]() IS25LE01GG IS25WE01GG Integrated Silicon Solution, Inc.- www.issi.com 174 Rev. A3 10/02/2025 8.70 IN BAND RESET OPERATION The device offers an additional feature of In-Band RESET function, which uses existing SPI signals to initiate a hardware reset, which is different from existing software reset/hardware reset (dedicated RESET# pin); - Existing software reset commands often depend on the Flash being in a particular mode before they are effective. This makes software based reset sequences depend on slave device and mode. - Dedicated RESET# pin requires additional pin over traditional 8-pins of SPI Flash device. Also it requires 1 more signal for reset operation. In Band-RESET operation requires 2-signal pins; CE# and IO0. • CE# is driven active low to select the SPI slave (note1) • Clock (SCK) remains stable in either a high or low state ….(note 2) • SI (DQ0) is driven low by the bus master, simultaneously with CE# going active low……(note 3) • CE# is driven inactive … (note 4) • Repeat the above 4 steps, each time alternating the state of SI (IO0). • After the fourth CE# pulse, the slave triggers its internal reset……..(note 5) Note 1 This powers up the SPI slave Note 2 This prevents any confusion with a command, as no command bits are transferred (clocked) Note 3 No SPI bus slave drives SI (IO0) during CE# low before a transition of clock (SCK). Slave streaming output active is not allowed until after the first edge of clock (SCK). Note 4 The slave captures the state of SI on the rising edge of CE# Note 5 SI (IO0) is low on the first CE#, high on the second, low on the third, high on the fourth … (This provides a 5h, unlike random noise) NOTE: This reset sequence is not intended to be used at normal power on, but to be used only when the device is not responding to the system. This reset sequence will be operational from any state that the device may be in. During the reset process, the device will ignore any chip select {command}. Once the sequence is completed the device will respond to normal operation e.g: provide a SFDP response. |
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