IS25LEG-RGLA2:P-TR datasheet(178/193 Pages) ISSI

部件名	IS25LEG-RGLA2:P-TR

功能描述	SERIAL FLASH MEMORY 166/133MHZ MULTI I/O SPI & QUAD I/O QPI DTR INTERFACE WITH ON-CHIP ECC

PDF	193 Pages

Scroll/Zoom	100%

制造商	ISSI [Integrated Silicon Solution, Inc]

网页	http://www.issi.com

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178 / 193 page

IS25LE01GG

IS25WE01GG

Integrated Silicon Solution, Inc.- www.issi.com

178

Rev. A3

10/02/2025

8.73 WRITE ECC REGISTER OPERATION (WRECC, B5h)

A Write ECC Register (WRECC) instruction is used to set bit [0] of ECC Register to “1” to disable ECC and clear

bit [0] to “0” to enable ECC. Only bit [0] is available for ECC register write operation. Write data for bit [47:1] is

ignored, so 1 byte write with bit [0] data is used for Write ECC Register operation.

Example:

Set bit [0] to “1” (Disable ECC): [FFh]

Clear bit [0] to “0” (Enable ECC): [00h]

Before the WRECC command can be accepted by the device, a Write Enable (WREN) command is required.

The WRECC command is entered by driving CE# low, followed by the instruction code and 8-bit data byte.

CE# must be driven high after the eighth bit of data has been latched in. As soon as CE# is driven high, the WRECC

operation is initiated.

Figure 8.160 Write ECC Register Sequence In SPI Mode

Instruction = B3h

CE#

SCK

...

Mode 3

Mode 0

Data In

Figure 8.161 Write ECC Register Sequence In QPI Mode

15h

Mode 3

Mode 0

7:4

3:0

CE#

SCK

IO[3:0]

Data In

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