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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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IS25LEG-RLLA2:P-TY 数据表(PDF) 31 Page - Integrated Silicon Solution, Inc |
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IS25LEG-RLLA2:P-TY 数据表(HTML) 31 Page - Integrated Silicon Solution, Inc |
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31 / 193 page  IS25LE01GG IS25WE01GG Integrated Silicon Solution, Inc.- www.issi.com 31 Rev. A3 10/02/2025 (IS25WE01GG) P[6:3] Dummy Cycles2,3 Fast Read5 0Bh/0Ch Fast Read Dual Output 3Bh/3Ch Fast Read Dual IO BBh/BCh Fast Read Quad Output 6Bh/6Ch Fast Read Quad IO EBh/ECh FRDTR 0Dh/0Eh FRDDTR BDh/BEh FRQDTR EDh/EEh SPI QPI SPI SPI SPI SPI, QPI SPI/QPI SPI4 SPI, QPI 0 Default1 133MHz 81MHz 133MHz 88MHz 120MHz 81MHz 80/58MHz 54MHz 58MHz 1 1 98MHz 23MHz 75MHz 52MHz 63MHz 23MHz 50/11MHz 23MHz 11MHz 2 2 110MHz 34MHz 84MHz 62MHz 72MHz 34MHz 63/21MHz 33MHz 21MHz 3 3 122MHz 46MHz 98MHz 75MHz 80MHz 46MHz 75/31MHz 43MHz 31MHz 4 4 133MHz 58MHz 104MHz 88MHz 88MHz 58MHz 80/42MHz 54MHz 42MHz 5 5 133MHz 69MHz 112MHz 98MHz 96MHz 69MHz 80/50MHz 62MHz 50MHz 6 6 133MHz 81MHz 120MHz 107MHz 104MHz 81MHz 80/58MHz 71MHz 58MHz 7 7 133MHz 90MHz 128MHz 115MHz 112MHz 90MHz 8064MHz 80MHz 64MHz 8 8 133MHz 98MHz 133MHz 123MHz 120MHz 98MHz 80/70MHz 80MHz 70MHz 9 9 133MHz 106MHz 133MHz 128MHz 127MHz 108MHz 80/75MHz 80MHz 75MHz 10 10 133MHz 114MHz 133MHz 133MHz 133MHz 116MHz 80/80MHz 80MHz 80MHz 11 11 133MHz 124MHz 133MHz 133MHz 133MHz 125MHz 80/80MHz 80MHz 80MHz 12 12 133MHz 133MHz 133MHz 133MHz 133MHz 131MHz 80/80MHz 80MHz 80MHz 13 13 133MHz 133MHz 133MHz 133MHz 133MHz 133MHz 80/80MHz 80MHz 80MHz 14 14 133MHz 133MHz 133MHz 133MHz 133MHz 133MHz 80/80MHz 80MHz 80MHz 15 15 133MHz 133MHz 133MHz 133MHz 133MHz 133MHz 80/80MHz 80MHz 80MHz Notes: 1. Default dummy cycles are as follows. Operation Command Dummy Cycles Comment SPI mode QPI mode SPI mode QPI mode Fast Read 0Bh/0Ch 0Bh/0Ch 8 6 RDUID, IRRD operations are also applied. Fast Read Dual Output 3Bh/3Ch - 8 - Fast Read Quad Output 6Bh/6Ch - 8 - Fast Read Dual IO BBh/BCh - 4 - Fast Read Quad IO EBh/ECh EBh/ECh 6 6 Fast Read DTR 0Dh/0Eh 0Dh/0Eh 8 6 Fast Read Dual IO DTR BDh/BEh - 4 - Fast Read Quad IO DTR EDh/EEh EDh/EEh 6 6 2. Enough number of dummy cycles must be applied to execute properly the AX read operation. 3. Must satisfy bus I/O contention. For instance, if the number of dummy cycles and AX bits cycles are same, then X must be Hi-Z. 4. QPI mode is not available for FRDDTR command. 5. RDUID, IRRD instructions are also applied. |
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