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TMS320F2811PBKA 数据表(PDF) 60 Page - Texas Instruments

部件名 TMS320F2811PBKA
功能描述  TMS320F281x Digital Signal Processors
PDF  174 Pages
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制造商  TI2 [Texas Instruments]
网页  https://www.ti.com
标志 TI2 - Texas Instruments

TMS320F2811PBKA 数据表(HTML) 60 Page - Texas Instruments

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8.12.5.11 External Interface Ready-on-Read Timing With One External Wait State
8.12.5.11.1 External Memory Interface Read Switching Characteristics (Ready-on-Read, 1 Wait State)
PARAMETER
MIN
MAX
UNIT
td(XCOH-XZCSL)
Delay time, XCLKOUT high to zone chip-select active-low
1
ns
td(XCOHL-XZCSH)
Delay time, XCLKOUT high/low to zone chip-select inactive-high
–2
3
ns
td(XCOH-XA)
Delay time, XCLKOUT high to address valid
2
ns
td(XCOHL-XRDL)
Delay time, XCLKOUT high/low to XRD active-low
1
ns
td(XCOHL-XRDH)
Delay time, XCLKOUT high/low to XRD inactive-high
–2
1
ns
th(XA)XZCSH
Hold time, address valid after zone chip-select inactive-high
(1)
ns
th(XA)XRD
Hold time, address valid after XRD inactive-high
(1)
ns
(1)
During inactive cycles, the XINTF address bus will always hold the last address put out on the bus. This includes alignment cycles.
8.12.5.11.2 External Memory Interface Read Timing Requirements (Ready-on-Read, 1 Wait State)
MIN
MAX
UNIT
ta(A)
Access time, read data from address valid
(LR + AR) – 14(1)
ns
ta(XRD)
Access time, read data valid from XRD active-low
AR – 12(1)
ns
tsu(XD)XRD
Setup time, read data valid before XRD strobe inactive-high
12
ns
th(XD)XRD
Hold time, read data valid after XRD inactive-high
0
ns
(1)
LR = Lead period, read access. AR = Active period, read access. See Table 8-3.
8.12.5.11.3 Synchronous XREADY Timing Requirements (Ready-on-Read, 1 Wait State)
MIN(1)
MAX
UNIT
tsu(XRDYsynchL)XCOHL
Setup time, XREADY (synchronous) low before XCLKOUT high/low
15
ns
th(XRDYsynchL)
Hold time, XREADY (synchronous) low
12
ns
te(XRDYsynchH)
Earliest time XREADY (synchronous) can go high before the sampling
XCLKOUT edge
3
ns
tsu(XRDYsynchH)XCOHL
Setup time, XREADY (synchronous) high before XCLKOUT high/low
15
ns
th(XRDYsynchH)XZCSH
Hold time, XREADY (synchronous) held high after zone chip-select high
0
ns
(1)
The first XREADY (synchronous) sample occurs with respect to E in Figure 8-29:
E = (XRDLEAD + XRDACTIVE) tc(XTIM)
When first sampled, if XREADY (synchronous) is found to be high, then the access will complete. If XREADY (synchronous) is found to
be low, it will be sampled again each tc(XTIM) until it is found to be high.
For each sample (n), the setup time (D) with respect to the beginning of the access can be calculated as:
D = (XRDLEAD + XRDACTIVE + n – 1) tc(XTIM) – tsu(XRDYsynchL)XCOHL
where n is the sample number (n = 1, 2, 3, and so forth).
8.12.5.11.4 Asynchronous XREADY Timing Requirements (Ready-on-Read, 1 Wait State)
MIN(1)
MAX
UNIT
tsu(XRDYAsynchL)XCOHL
Setup time, XREADY (asynchronous) low before XCLKOUT high/low
11
ns
th(XRDYAsynchL)
Hold time, XREADY (asynchronous) low
8
ns
te(XRDYAsynchH)
Earliest time XREADY (asynchronous) can go high before the sampling
XCLKOUT edge
3
ns
tsu(XRDYAsynchH)XCOHL
Setup time, XREADY (asynchronous) high before XCLKOUT high/low
11
ns
th(XRDYAsynchH)XZCSH
Hold time, XREADY (asynchronous) held high after zone chip-select high
0
ns
(1)
The first XREADY (asynchronous) sample occurs with respect to E in Figure 8-30:
E = (XRDLEAD + XRDACTIVE – 2) tc(XTIM)
When first sampled, if XREADY (asynchronous) is found to be high, then the access will complete. If XREADY (asynchronous) is found
to be low, it will be sampled again each tc(XTIM) until it is found to be high.
For each sample, setup time from the beginning of the access can be calculated as:
D = (XRDLEAD + XRDACTIVE – 3 + n) tc(XTIM) – tsu(XRDYAsynchL)XCOHL
TMS320F2810, TMS320F2810-Q1, TMS320F2811, TMS320F2811-Q1
TMS320F2812, TMS320F2812-Q1
SPRS174V – APRIL 2001 – REVISED FEBRUARY 2021
www.ti.com
60
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Product Folder Links: TMS320F2810 TMS320F2810-Q1 TMS320F2811 TMS320F2811-Q1 TMS320F2812
TMS320F2812-Q1



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