i

i

1

f

2 Z C

p

=

ƒ

5

6

7

8

9

10

INNR

PLIMIT

GVDD

GAIN/SLV

GND

2

1

1

2

C5

1 F

µ

2

1

51 k

R1

51 k

R2

13

TPA3128D2, TPA3129D2

www.ti.com

SLOS941C – MAY 2016 – REVISED JANUARY 2018

Product Folder Links: TPA3128D2 TPA3129D2

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Copyright © 2016–2018, Texas Instruments Incorporated

7.3 Feature Description

(1)

Resistor tolerance should be 5% or better.

7.3.1 Gain Setting and Master and Slave

The gain of the TPA312xD2 is set by the voltage divider connected to the GAIN/SLV control pin. Master or Slave

mode is also controlled by the same pin. An internal ADC is used to detect the 8 input states. The first four

stages sets the GAIN in Master mode in gains of 20, 26, 32, 36 dB respectively, while the next four stages sets

the GAIN in Slave mode in gains of 20, 26, 32, 36 dB respectively. The gain setting is latched during power-up

and cannot be changed while device is powered. Table 1 lists the recommended resistor values and the state

and gain:

Table 1. Gain and Master/Slave

MASTER / SLAVE

MODE

GAIN

R1 (to GND)(1)

R2 (to GVDD)(1)

INPUT IMPEDANCE

Master

20 dB

5.6 kΩ

OPEN

60 kΩ

Master

26 dB

20 kΩ

100 kΩ

30 kΩ

Master

32 dB

39 kΩ

100 kΩ

15 kΩ

Master

36 dB

47 kΩ

75 kΩ

9 kΩ

Slave

20 dB

51 kΩ

51 kΩ

60 kΩ

Slave

26 dB

75 kΩ

47 kΩ

30 kΩ

Slave

32 dB

100 kΩ

39 kΩ

15 kΩ

Slave

36 dB

100 kΩ

16 kΩ

9 kΩ

Figure 25. Gain, Master/Slave

In Master mode, SYNC terminal is an output, in Slave mode, SYNC terminal is an input for a clock input. TTL

logic levels with compliance to GVDD.

7.3.2 Input Impedance

The TPA31xxD2 input stage is a fully differential input stage and the input impedance changes with the gain

setting from 9 k

Ω at 36 dB gain to 60 kΩ at 20 dB gain. Table 1 lists the values from min to max gain. The

tolerance of the input resistor value is ±20% so the minimum value will be higher than 7.2 k

Ω. The inputs must

be AC-coupled to minimize the output dc-offset and ensure correct ramping of the output voltages during power-

ON and power-OFF. The input ac-coupling capacitor together with the input impedance forms a high-pass filter

with the following cut-off frequency:

(1)

If a flat bass response is required down to 20 Hz the recommended cut-off frequency is a tenth of that, 2 Hz.

Table 2 lists the recommended ac-couplings capacitors for each gain step. If a –3-dB capacitor is accepted at 20

Hz 10 times lower capacitors can used – for example, a 1-µF capacitor can be used.