TPL0102 datasheet(21/48 Pages) TI2

21 / 48 page

SCL

SDA

MSB

Bit

LSB

Byte: 1010 1010 ( 0xAAh )

SDA line stable while SCL line is high

ACK

SCL

SDA

STAR T

Condition

STOP

Condition

Data Transfer

TPL0102

www.ti.com

SLIS134C – MARCH 2011 – REVISED SEPTEMBER 2015

Product Folder Links: TPL0102

Submit Documentation Feedback

Programming with I

2C (continued)

Figure 22. Definition of START and STOP Conditions

7.5.1.3 Data Validity and Byte Formation

One data bit is transferred during each clock pulse of the SCL. One byte is comprised of eight bits on the SDA

line. A byte may either be a device address, register address, or data written to or read from a slave.

Data is transferred Most Significant Bit (MSB) first. Any number of data bytes can be transferred from the master

to slave between the START and STOP conditions. Data on the SDA line must remain stable during the high

phase of the clock period, as changes in the data line when the SCL is high are interpreted as control commands

(START or STOP).

Figure 23. Definition of Byte Formation

7.5.1.4 Acknowledge (ACK) and Not Acknowledge (NACK)

Each byte is followed by one ACK bit from the receiver. The ACK bit allows the receiver to communicate to the

transmitter that the byte was successfully received and another byte may be sent.

The transmitter must release the SDA line before the receiver can send the ACK bit. To send an ACK bit, the

receiver shall pull down the SDA line during the low phase of the ACK/NACK-related clock period (period 9), so

that the SDA line is stable low during the high phase of the ACK/NACK-related clock period. Setup and hold

times must be taken into account.

TPL0102 数据表(PDF) 21 Page - Texas Instruments

TPL0102 数据表(HTML) 21 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48

数据表下载