HCC/HCF4014B

HCC/HCF4021B

8-STAGE STATIC SHIFT REGISTERS

DESCRIPTION

.

MEDIUM-SPEED OPERATION-12MHz (typ.)

.

FULLY STATIC OPERATION

.

8 MASTER-SLAVE FLIP-FLOPS PLUS OUT-

PUT BUFFERING AND CONTROL GATING

.

QUIESCENT CURRENT SPECIFIED TO 20V

FOR HCC DEVICE

.

5V, 10V AND 15V PARAMETRIC RATINGS

.

INPUT CURRENT OF 100nA AT 18V AND 25

°C

FOR HCC DEVICE

.

100% TESTED FOR QUIESCENT CURRENT

.

MEETS ALL REQUIREMENTS OF JEDEC TEN-

TATIVE STANDARD N

o

13A, ”STANDARD

SPECIFICATIONS FOR DESCRIPTION OF ”B”

SERIES CMOS DEVICES”

November 1996

The HCC4014B, HCC4021B (extended temperatu-

re range) and the HCF4014B, HCF4021B (interme-

diate temperature range) are monolithic integrated

circuits, available in 16-lead dual in-line plastic or ce-

ramic package and plastic micro package. The

HCC/HCF4014B and HCC/HCF4021B series types

are 8-stage parallel-or serial-input/serial-output re-

gisters having common CLOCK and PARAL-

LEL/SERIAL CONTROL inputs, a single SERIAL

data input, and individual parallel ”JAM” inputs to

each register stage. Each register stage is a D type,

master-slave flip-flop in addition to an output from

stage 8, ”Q” outputs are also available from stages

6 and 7. Parallel as well as serial entry is made into

the register synchronously with the positive clock li-

ne transition in the HCC/HCF4014B. In the

HCC/HCF4021B serial entry is synchronous with

the clock but parallel entry is asynchronous. In both

types, entry is controlled by the PARALLEL/SERIAL

CONTROL input. When the PARALLEL/SERIAL

CONTROL input is low, data is serially shifted into

the 8-stage register synchronously with the positive

transition of the clock line. When the PARAL-

LEL/SERIAL CONTROL input is high, data is jam-

med into the 8-stage register via the parallel input

EY

(Plastic Package)

F

(Ceramic Package)

C1

(Plastic Chip Carrier)

ORDER CODES :

HCC40XXBF

HCF40XXBM1

HCF40XXBEY

HCF40XXBC1

PIN CONNECTIONS

4014B

SYNCHRONOUS PARALLEL OR

SERIAL INPUT/SERIAL OUTPUT

4021B

ASYNCHRONOUS PARALLEL

INPUT OR SYNCHRONOUS

SERIAL INPUT/SERIAL OUTPUT

lines and synchronous with the positive transition of

the clock line. In the HCC/HCF4021B, the CLOCK

input of the internal stage is ”forced” when asynchro-

nous parallel entry is made. Register expansion

using multiple package is permitted.

M1

(Micro Package)

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