−2

0

2

4

6

8

−3m

−2m

−1m

0

1m

2m

3m

4m

5m

ENx

OUTx

Time (s)

VIN = 5 V,CLx = 1 µF, RLoadx = 5 Ω, TPS2062C

−2m

0

2m

4m

6m

8m

10m 12m 14m 16m 18m

−8

−6

−4

−2

0

2

4

6

8

−0.5

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

OUTx

ENx

FLTx

Time (s)

IOUTx

V

IN = 5 V, C

= 150 F, R

= 10

, TPS2062C

Lx

Loadx

TPS2052C, TPS2062C, TPS2062C-2, TPS2066C, TPS2066C-2

TPS2060C, TPS2064C, TPS2064C-2, TPS2002C, TPS2003C

SLVSAX6H – OCTOBER 2011 – REVISED DECEMBER 2015

www.ti.com

Typical Application (continued)

10.2.1 Design Requirements

Table 3 shows the design requirements for the typical application.

Table 3. Design Parameters

PARAMETER

VALUE

Input voltage

5 V

Output voltage 1

5 V

Output voltage 2

5 V

Current limit

1 A

10.2.2 Detailed Design Procedure

10.2.2.1 Input and Output Capacitance

Input and output capacitance improves the performance of the device. For all applications, TI recommends

placing a 0.1-µF or greater ceramic bypass capacitor between IN and GND as close as possible to the device for

local noise de-coupling. The actual capacitance should be optimized for the particular application. This

precaution reduces ringing on the input due to power-supply transients. Additional input capacitance may be

needed on the input to reduce the overshoot voltage from exceeding the absolute maximum voltage of the

device during heavy transients.

A 120-µF minimum output capacitance is required when implementing USB standard applications. Typically this

uses a 150-µF electrolytic capacitor. If the application does not require 120 µF of output capacitance, a minimum

of 10-µF ceramic capacitor on the output is recommended to reduce the transient negative voltage on OUTx pin

caused by load inductance during a short circuit. The transient negative voltage should be less than 1.5 V for

10 µs.

10.2.3 Application Curves

Figure 33. TPS2062C Enable/Disable into 10-

Ω Load

Figure 32. TPS2062C Turnon Delay and

Rise Time With 1-

μF Load

20

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