LOGIC DIAGRAM AND TRUTH TABLE

v = LEVEL CHANGE

•

=

INVALID CONDI-

INPUTS

OUT

v

v

DQ

00

00

0

•

X0

11

11

1

•

FOR REGISTER INPUT-LEVELS AND RESULTING REGISTER OPERATION

”A”

Enable

P/S

A/B

A/S

Operation*

0

0

0

X

Serial Mode ; Synch. Serial Data Input, ”A” Parallel Data Outputs Disabled

0

0

1

X

Serial Mode ; Synch. Serial Data Input, ”B” Parallel Data Output

0

1

0

0

Parallel Mode ; ”B” Synch. Parallel Data Inputs, ”A” Parallel Data Outputs

Disabled

0

1

0

1

Parallel Mode ; ”B” Asynch. Parallel Data Inputs, ”A” Parallel Data Outputs

Disabled

0

1

1

0

Parallel Mode ; ”A” Parallel Data Inputs Disabled, ”B” Parallel Data Outputs,

Synch. Data Recirculation

0

1

1

1

Parallel Mode ; ”A” Parallel Data Inputs Disabled, ”B” Parallel Data Outputs,

Asynch. Data Recirculation

1

0

0

X

Serial Mode ; Synch. Serial Data Input, ”A” Parallel Data Output

1

0

1

X

Serial Mode ; Synch. Serial Data Input, ”B” Parallel Data Output

1

1

0

0

Parallel Mode ; ”B” Synch. Parallel Data Input, ”A” Parallel Data Output

1

1

0

1

Parallel Mode ; ”B” Asynch. Parallel Data Input, ”A” Parallel Data Output

1

1

1

0

Parallel Mode ; ”A” Synch. Parallel Data Input, ”B” Parallel Data Output

1

1

1

1

Parallel Mode ; ”A” Asynch. Parallel Data Input, ”B” Parallel Data Outpu

* Outputs change at positive transition of clock in the serial mode and when the A/S control inputs is ”low” in the parallel

mode.

REGISTER STAGE (1 of 8 stages)

HCC/HCF4034B

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